Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory

A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique

“…VDD of 0.75 V is chosen for energy saving. Besides on, a capacitor of 1024 f F is assumed in BL/DBL, which is equivalent to 1024 cells with 1 f F loading for each cell [30]. For comparison, the previous techniques such as [10,14,17] are also simulated in the 40 nm SOI technology with the same ReRAM model, amplifiers and latch.…”

Sensing schemes for STT-MRAMs structured with high TMR in low RA MTJs

“…However, the reading operation of a VSenseAmp can be faster compared to CSenseAmp when the variations of threshold voltages V T H of the CMOS devices are greater than 12mV [16]. In fact, the variations of V T H are 30mV or more in deep sub-micron technologies [17], such as in 65nm CMOS technology nodes also used in this work [8,18,19,17,20].…”

“…However, there are some efforts on circuit level based on equalizing the differences in parasitic resistance between BLs [8]. This latter approach improves the read access time [18] of well-defined reference resistance cells, which are self-reference cells [23], self reference cells with two transistors and two MTJs [17], dynamic data dependent reference cells [18,24,19], reference cells at only R P state [8], and locating reference cells close to data cells [18]. At the same time, these works address the vulnerabilities of the sensing scheme of the STT-MRAM.…”

“…However, the use of simple current mirror circuitry in the sensing scheme may increase current mismatches in the BLs and REFLs [8,24,19], and the dynamic data dependent sensing schemes [18,24,19] are a good solution to increase the SM, but the power consumption of these schemes increases due to the use of two cross-coupled latch SenseAmps [18,24] and a differential amplifier [19]. In addition, these two latch circuits have a high sensitivity into the mismatches [19]. The realization of STT-MRAM cell arrays with two transistors and two MTJs [17] achieves low SM, whereas it suffers from high cost and high area.…”

“…We compared the read performance of the CSenseAmp 305 [8], our proposed VSenseAmp, and some SenseAmp designs in literature in terms of BER, power, speed, and area perspective. We perform the speed and power comparisons of our work with the reference works [18,19,23] taking into account the bit lines and the reference lines 310 parasitic capacitance values of 50fF, and these simulation results are obtained from Monte Carlo analyses including CMOS device variations (TSMC 65nm physical parameters) and MTJ device variations. Moreover, intuitively speed and power performances of an MRAM cell can be 315 better with MTJ or CMOS device level innovations, such used MTJ devices have lower switching power and a perpendicularly magnetized with low-resistance area product, proposed in [6,3,4].…”