Dynamic Energy Optimization in Chip Multiprocessors Using Deep Neural Networks

Moghaddam, Milad Ghorbani; Guan, Wenkai; Ababei, Cristinel

doi:10.1109/tmscs.2018.2870438

Cited by 7 publications

(3 citation statements)

References 17 publications

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“…Dark (power gating) silicon and dim (dynamic voltage/frequency scaling) silicon are two techniques to achieve energy efficiency in Many-Core chips [ 30 , 31 , 32 ]. Since power depends on voltage and frequency directly, the NoC must dynamically configure links and nodes depending on the traffic demands to extend chip power and thermal budgets, by scaling node-voltage and link-width, or power gating.…”

Section: The Motivation For An Sdnoc Approachmentioning

confidence: 99%

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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Section: The Motivation For An Sdnoc Approachmentioning

confidence: 99%

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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“…Milad et al 15 examine using deep neural network (DNN) models in chip multiprocessor systems for energy optimization. They introduced a three‐phase dynamic power management algorithm, and the training data are collected with several selected instrumented benchmarks.…”

Section: Literature Surveymentioning

confidence: 99%

Dynamic machine learning‐based heuristic energy optimization approach on multicore architecture

Sundaresan

Durai

2019

Computational Intelligence

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In the present era, energy is progressively turning into the major limitation in designing multicore chips. However, power and performance are the primary segments of energy, which are contrarily correlated in multicore architectures. This research primarily focused on optimizing energy level of multicore chips using parallel workloads by utilizing either power or execution advancement based on machine learning computation on dynamic programming. To do as such, the novel dynamic machine learning‐based heuristic energy optimization (DML‐HEO) algorithm has been designed and developed in this research on application‐specific controllers to optimize energy‐level on multicore architecture. Here DML‐HEO is implemented on the controller to maximize the execution inside a fixed power spending plan or to limit the expended capacity to accomplish a similar pattern execution. The controller is additionally scalable as it does not bring about critical overhead due to the increase in quantity of cores. The strategy has been assessed utilizing controllers on a full‐framework test system at lab‐scale analysis. The experimental results demonstrate that our proposed DML‐HEO system shows improving performance than the traditional system.

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“…A problem of allocating optical links for connecting automatic circuit breakers in a utility power grid has been solved using a multi-objective genetic algorithm (NSGA-II) [17] in [18]. Energy optimization under performance constraints in chip multiprocessor systems has been addressed in [19] where deep neural network is shown to outperform reinforcement learning (e.g., [20]) and Kalman filtering (e.g., [21]). Training a neural network on weather and turbine data, Google's DeepMind system predicted "wind power output 36 hours ahead of actual generation ... [and] boosted the value of ... wind energy by roughly 20 percent" [22].…”

Section: Introductionmentioning

confidence: 99%

Proton Exchange Membrane Fuel Cell Stack Design Optimization Using an Improved Jaya Algorithm

Chakraborty

2019

Energies

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Fuel cell stack configuration optimization is known to be a problem that, in addition to presenting engineering challenges, is computationally hard. This paper presents an improved computational heuristic for solving the problem. The problem addressed in this paper is one of constrained optimization, where the goal is to seek optimal (or near-optimal) values of (i) the number of proton exchange membrane fuel cells (PEMFCs) to be connected in series to form a group, (ii) the number of such groups to be connected in parallel, and (iii) the cell area, such that the PEMFC assembly delivers the rated voltage at the rated power while the cost of building the assembly is as low as possible. Simulation results show that the proposed method outperforms four of the best-known methods in the literature. The improvement in performance afforded by the proposed algorithm is validated with statistical tests of significance.

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Dynamic Energy Optimization in Chip Multiprocessors Using Deep Neural Networks

Cited by 7 publications

References 17 publications

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Dynamic machine learning‐based heuristic energy optimization approach on multicore architecture

Proton Exchange Membrane Fuel Cell Stack Design Optimization Using an Improved Jaya Algorithm

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