Dynamic MAC-based architecture of artificial neural networks suitable for hardware implementation on FPGAs

Nedjah, Nadia; Silva, R. M. da; Mourelle, Luiza Macedo; Silva, M. V. C. da

doi:10.1016/j.neucom.2008.06.027

Cited by 39 publications

(28 citation statements)

References 4 publications

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“…Unlike many FPGA-based methods that focus on increasing the hardware performance but without a theoretical study of biological dynamics at the network level (Cassidy et al, 2011;Gadea et al, 2000;Gomperts et al;Nedjah et al, 2009), we highlighted the dynamic behaviors of the FNN in the present study. Both the normal and the Parkinsonian state of the BG can be emulated on our hardware platform thanks to its flexibility and the comprehensive consideration of the biological states during the design process.…”

Section: Discussionmentioning

confidence: 99%

Cost-efficient FPGA implementation of basal ganglia and their Parkinsonian analysis

Yang

Wang

et al. 2015

Neural Networks

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Section: Discussionmentioning

confidence: 99%

Cost-efficient FPGA implementation of basal ganglia and their Parkinsonian analysis

Yang

Wang

et al. 2015

Neural Networks

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“…Applying the superposition theorem 5 and associating the resistances to the required synaptic weights, we have (24), which yields the circuit's and neuron's output f for the linear part of operation. …”

Section: Fixed Synaptic Weightsmentioning

confidence: 99%

“…; x m have an in°uence on the computation of the positive synaptic weights w þ i , as shown in (26). With respect to (24), the implementation of a negative bias, b À , may be performed…”

Section: Fixed Synaptic Weightsmentioning

confidence: 99%

Analog Hardware Implementations of Artificial Neural Networks

Nedjah

Silva

Mourelle

2011

J CIRCUIT SYST COMP

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There are several possible implementations of arti¯cial neural network that are based either on software or hardware systems. Software implementations are rather ine±cient due to the fact that the intrinsic parallelism of the underlying computation is usually not taken advantage of in a mono-processor kind of computing system. Existing hardware implementations of ANNs are e±cient as the dedicated datapath used is optimized and the hardware is usually parallel. Hardware implementations of ANNs may be either digital, analog, or even hybrid. Digital implementations of ANNs tend to be of high complexity, thus of high cost, and somehow imprecise due to the use of lookup table for the activation function. On the other hand, analog implementation of ANNs are generally very simple and much more precise. In this paper, we focus on possible analog implementations of ANNs. The neuron is based on a simple operational ampli¯er. The reviewed implementations allow for the use of both negative and positive synaptic weights. An alternative implementation permits the realization of the training process.

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“…In addition, the numeric process behind this model is too complex. In other words, it consists of massively parallel nonlinear computations . Thus, the process needed high speed in real‐time applications, which can be realized provided that the network uses parallel hardware structure …”

Section: Introductionmentioning

confidence: 99%

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

Alçın

Koyuncu

Tuna

et al. 2018

Circuit Theory & Apps

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Summary It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high‐speed TRNG based on chaos and ANN implemented in a Xilinx field‐programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan‐Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140‐1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications.

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Dynamic MAC-based architecture of artificial neural networks suitable for hardware implementation on FPGAs

Cited by 39 publications

References 4 publications

Cost-efficient FPGA implementation of basal ganglia and their Parkinsonian analysis

Cost-efficient FPGA implementation of basal ganglia and their Parkinsonian analysis

Analog Hardware Implementations of Artificial Neural Networks

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

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