Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375)
DOI: 10.1109/fpga.1999.803687
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Dynamic precision management for loop computations on reconfigurable architectures

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Cited by 25 publications
(14 citation statements)
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“…Dynamically reconfigurable architectures or systems can adapt their function and/or structure to suit the changing needs of a computation during run time (e.g., [2,3]). A principle problem of dynamically reconfigurable systems is the tradeoff between flexibility and the amount of information needed for reconfiguration to define the new state of the system.…”
Section: Introductionmentioning
confidence: 99%
“…Dynamically reconfigurable architectures or systems can adapt their function and/or structure to suit the changing needs of a computation during run time (e.g., [2,3]). A principle problem of dynamically reconfigurable systems is the tradeoff between flexibility and the amount of information needed for reconfiguration to define the new state of the system.…”
Section: Introductionmentioning
confidence: 99%
“…As for dynamic techniques, Bondalapati and Prasanna [1999] presents a technique that dynamically reconfigures the functional units in an FPGA when more precision is needed for integer operands inside the loops. They keep multiple precision configurations and reconfigure the FPGA as precision requirements change.…”
Section: Related Workmentioning
confidence: 99%
“…1) Algorithm analysis layer. The common tasks associated with this layer include: extracting compiler-controlled memory management [38], [39], pointer analysis for hardware synthesis [37], loop transformations for hardware generation [7], [11], [24], precision analysis [4], [6], [35], data-structure transformations, and architecture selection. This layer is currently handled manually, i.e., all algorithmic transformations are done by the programmer.…”
Section: A Stream Compiler (Asc)mentioning
confidence: 99%