Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background-pattern Dependencies in Pure Memristor Array

Shin, SangHak; Byeon, Sang-Don; Song, JeaSang; Truong, S.; Mo, Huaping; Kim, Deajeong; Min, Kyeong‐Sik

doi:10.5573/jsts.2015.15.6.685

Cited by 7 publications

(12 citation statements)

References 17 publications

(22 reference statements)

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“…However, the impact wire resistance in crossbar is inevitable. It becomes more serious as the array size increases [25]. Wire resistance is modeled by small-value resistors lying on the vertical lines and the horizontal lines, as shown in Figure 3.…”

Section: Methodsmentioning

confidence: 99%

“…In a memristor crossbar array, some amount of voltage drop can be caused by parasitic resistance, also known as wire resistance along the row and the column lines [19,[24][25][26][27][28]. Hereinafter "wire resistance" and "parasitic resistance" are used interchangeably.…”

Section: Introductionmentioning

confidence: 99%

“…The impact of wire resistance becomes inevitable when the array size increases [22]. To mitigate the impact of wire resistance, several interesting schemes were proposed [25][26][27][28]. A design methodology has been proposed to reduce the impact of wire resistance in a one-selector-one resistive device (1S1R) crossbar array [27].…”

Section: Introductionmentioning

confidence: 99%

“…The proposed design methodology seems to be complicated since the physical specification of the devices must be considered [27]. Another approach to deal with the wire resistance is to use a dynamic reference scheme [25]. The read operation is performed with two steps associated with a special reading circuit.…”

Section: Introductionmentioning

confidence: 99%

“…The read operation is performed with two steps associated with a special reading circuit. [25]. These proposed schemes are effective when they are applied to a memristor crossbar array, in which memristors are used as binary switches between two distinct high and low resistance states (HRS (High Resistance State) and LRS (Low Resistance State)).…”

Section: Introductionmentioning

confidence: 99%

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A Parasitic Resistance-Adapted Programming Scheme for Memristor Crossbar-Based Neuromorphic Computing Systems

Truong

2019

Materials

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Memristor crossbar arrays without selector devices, such as complementary-metal oxide semiconductor (CMOS) devices, are a potential for realizing neuromorphic computing systems. However, wire resistance of metal wires is one of the factors that degrade the performance of memristor crossbar circuits. In this work, we propose a wire resistance modeling method and a parasitic resistance-adapted programming scheme to reduce the impact of wire resistance in a memristor crossbar-based neuromorphic computing system. The equivalent wire resistances for the cells are estimated by analyzing the crossbar circuit using the superposition theorem. For the conventional programming scheme, the connection matrix composed of the target memristance values is used for crossbar array programming. In the proposed parasitic resistance-adapted programming scheme, the connection matrix is updated before it is used for crossbar array programming to compensate the equivalent wire resistance. The updated connection matrix is obtained by subtracting the equivalent connection matrix from the original connection matrix. The circuit simulations are performed to test the proposed wire resistance modeling method and the parasitic resistance-adapted programming scheme. The simulation results showed that the discrepancy of the output voltages of the crossbar between the conventional wire resistance modeling method and the proposed wire resistance modeling method is as low as 2.9% when wire resistance varied from 0.5 to 3.0 Ω. The recognition rate of the memristor crossbar with the conventional programming scheme is 99%, 95%, 81%, and 65% when wire resistance is set to be 1.5, 2.0, 2.5, and 3.0 Ω, respectively. By contrast, the memristor crossbar with the proposed parasitic resistance-adapted programming scheme can maintain the recognition as high as 100% when wire resistance is as high as 3.0 Ω.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Parasitic Resistance-Adapted Programming Scheme for Memristor Crossbar-Based Neuromorphic Computing Systems

Truong

2019

Materials

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Analysis of the Impact of Wire Resistance on Nano-scale Memristor Crossbar Array Implementing Perceptron Neural Network

Truong

2020

IOP Conf. Ser.: Mater. Sci. Eng.

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In this work, the impact of wire resistance in pure memristor crossbar array is mathematically analysed and verified by the circuit simulation. The memristor crossbar without CMOS device is utilized for application of character image recognition, in which wire resistance is presented. Memristor crossbar circuit is analysed separately with respect to wire resistance on vertical line and wire resistance on horizontal line. The result shows that wire resistance on vertical line can be eliminated because they can be self-compensated. The simulation result agrees with the analysis. The variation of output voltage caused by wire resistance less affect the recognition rate of memristor circuit. On the other hand, when wire resistance on horizontal line is assumed to be 2.5Ω. The output voltages are varied remarkably. Such variation of output voltage degrades the recognition rate of memristor crossbar circuit. The interesting phenomenon is also investigated. The column that is close to the first column has less variation of output voltage, whereas the one that is far from the first column has much variation of output voltage. The result can be used in improving the memristor crossbar architecture, which can tolerate the impact of wire resistance. For example, if we want to increase the size of crossbar, we should increase the number of rows, rather than the number of columns.

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Quantization, training, parasitic resistance correction, and programming techniques of memristor-crossbar neural networks for edge intelligence

Nguyen

et al. 2022

Neuromorph. Comput. Eng.

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In Internet-of-Things (IoT) era, edge intelligence is critical for overcoming the communication and computing energy crisis, which is unavoidable if cloud computing is used exclusively. Memristor crossbars with in-memory computing may be suitable for realizing edge intelligence hardware. They can perform both memory and computing functions, allowing for the development of low-power computing architectures that go beyond the Von Neumann computer. For implementing edge-intelligence hardware with memristor crossbars, in this paper, we review various techniques such as quantization, training, parasitic resistance correction, and low-power crossbar programming, and so on. In particular, memristor crossbars can be considered to realize quantized neural networks with binary and ternary synapses. For preventing memristor defects from degrading edge intelligence performance, chip-in-the-loop training can be useful when training memristor crossbars. Another undesirable effect in memristor crossbars is parasitic resistances such as source, line, and neuron resistance, which worsens as crossbar size increases. Various circuit and software techniques can compensate for parasitic resistances like source, line, and neuron resistance. Finally, we discuss an energy-efficient programming method for updating synaptic weights in memristor crossbars, which is needed for learning the edge devices.

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Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background-pattern Dependencies in Pure Memristor Array

Cited by 7 publications

References 17 publications

A Parasitic Resistance-Adapted Programming Scheme for Memristor Crossbar-Based Neuromorphic Computing Systems

A Parasitic Resistance-Adapted Programming Scheme for Memristor Crossbar-Based Neuromorphic Computing Systems

Analysis of the Impact of Wire Resistance on Nano-scale Memristor Crossbar Array Implementing Perceptron Neural Network

Quantization, training, parasitic resistance correction, and programming techniques of memristor-crossbar neural networks for edge intelligence

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