Dynamic resizing of superscalar datapath components for energy efficiency

Ponomarev, Dmitry; Küçük, Gürhan; Ghose, K.

doi:10.1109/tc.2006.23

Cited by 26 publications

(16 citation statements)

References 15 publications

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“…Our goal is to share them across multiple cores with minimal impact on access latency, the number of ports, and the overall design. We take advantage of a modular ROB (and register file) design proposed in [25] which is shown to be effective in reducing the power and complexity of a multi-ported 2D SRAM structure. Our baseline multi-ported ROB/RF is implemented as a number of independent partitions.…”

Section: Reorder Buffer and Register Filementioning

confidence: 99%

Dynamically heterogeneous cores through 3D resource pooling

Homayoun

Kontorinis

Shayan

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

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Section: Reorder Buffer and Register Filementioning

confidence: 99%

Dynamically heterogeneous cores through 3D resource pooling

Homayoun

Kontorinis

Shayan

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

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“…A state transition out of some state s is controlled by either an action a ∈ A or a configuration change c ∈ C. Any state transition takes a certain amount of time to complete, where this latency overhead ranges from several clock cycles to hundreds of milli-seconds. A typical microarchitecture re-configuration latency, the duration between the time a decision is made to change the micro-architectural configuration and the time of actual configuration, takes up to tens of clock cycles [16]. Thus, a state transition time in the CTMDP model of the processor takes τ(s, s') time (= max (τ DVFS ,…”

Section: Modeling the Processor Statementioning

confidence: 99%

Stochastic modeling of a thermally-managed multi-core system

Jung

Peng

Pedram

2008

Proceedings of the 45th Annual Design Automation Conference

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Achieving high performance under a peak temperature limit is a first-order concern for VLSI designers. This paper presents a new abstract model of a thermally-managed system, where a stochastic process model is employed to capture the system performance and thermal behavior. We formulate the problem of dynamic thermal management (DTM) as the problem of minimizing the energy cost of the system for a given level of performance under a peak temperature constraint by using a controllable Markovian decision process (MDP) model. The key rationale for utilizing MDP for solving the DTM problem is to manage the stochastic behavior of the temperature states of the system under online re-configuration of its micro-architecture and/or dynamic voltage-frequency scaling. Experimental results demonstrate the effectiveness of the modeling framework and the proposed DTM technique.

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“…Adaptive front-end throttling is orthogonal to, and can even leverage, most existing techniques, providing even greater savings. For example, fetch gating based on branch prediction confidence [6,49] and dynamic issue queue, reorder buffer, and load/store queue re-sizing [8,14,26,54,57] can be applied together with adaptive front-end throttling to achieve greater savings. Third, previous work either does not have a direct way to quantify the overhead of the throttling technique and the resulting energy savings, or gets this information relying on architecture-level modeling frameworks, such as Wattch [13] and McPAT [45], which are known to have limited accuracy.…”

Section: Discussionmentioning

confidence: 99%

“…Prior works [8,9,14,23,26,36,49,50,54,57] have proposed various energy-saving techniques that dynamically allocate datapath resources according to the needs of applications. These energysaving techniques suffer from two problems.…”

Section: Dynamic Core Scalingmentioning

confidence: 99%

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Scrutinizing Resource Utilization for High Performance and Low Energy Computation

Zhang

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Modern processors often suffer from inefficient resource utilization, which leads to inferior performance and energy efficiency. This dissertation scrutinizes the utilization of datapath and cache resources in superscalar processors for opportunities to improve performance and energy efficiency.Traditional superscalar processors usually employ a one-size-fits-all design approach that allocates a fixed amount of resources for all applications at all times to deliver the best overall performance. However, the one-size-fits-all approach is not always energy efficient, because both the application behavior and the use scenario are changing all the time and the demand for processor resources is also changing accordingly.To improve the utilization of datapath resources, this dissertation proposes an adaptive processor that dynamically allocates datapath resources based on the needs of applications and use scenarios. The adaptive processor is applied to two use cases to improve energy efficiency. In the first use case (front-end throttling (FET)), the adaptive processor dynamically throttles the frontend instruction delivery bandwidth as program behavior changes to optimize a target metric, being performance, energy, or an arbitrary trade-off between them. In the second use case (dynamic core scaling (DCS)), the adaptive processor extends performance-energy tradeoff capabilities in superscalar processors by scaling datapath resource rather than voltage. The adaptive processor ensures that programs run at a given percentage of their maximum speed and, at the same time, minimizes energy consumption by dynamically adjusting the active superscalar datapath resources. DCS is more effective in performance-energy tradeoffs than DVFS at the high performance end. When used together with DVFS, DCS significantly extends the range of performance-energy tradeoffs.Caches also suffer from inefficient utilization in modern processors. To minimize the access iv v latency of set-associative caches, the data in all ways are read out in parallel with the tag lookup.However, this is energy inefficient, as only the data from the matching way is used and the others are discarded. To improve the utilization of the L1 instruction cache, this dissertation proposes an early tag lookup (ETL) technique for L1 instruction caches that determines the matching way one cycle earlier than the cache access, so that only the matching data way need to be accessed. ETL incurs no performance penalty and insignificant hardware overhead, but dramatically reduces the read energy of L1 instruction cache.For memory intensive workloads, caches often suffer from thrashing, i.e., high-reuse blocks evicting each other from the cache due to the lack of space. To reduce thrashing, only a fraction of the working set should be kept in the cache, so that at least this fraction stays longer in the cache to enable reuse before eviction. However, prior insertion policies take an ad hoc approach to selecting that fraction, e.g., inserting blocks with high priority at ...

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Dynamic resizing of superscalar datapath components for energy efficiency

Cited by 26 publications

References 15 publications

Dynamically heterogeneous cores through 3D resource pooling

Dynamically heterogeneous cores through 3D resource pooling

Stochastic modeling of a thermally-managed multi-core system

Scrutinizing Resource Utilization for High Performance and Low Energy Computation

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