Dynamic scan clock control for test time reduction maintaining peak power limit

Abstract

Abstract-We dynamically monitor per cycle scan activity to speed up the scan clock for low activity cycles without exceeding the specified peak power budget. The activity monitor is implemented either as on-chip hardware or through presimulated and stored test data. In either case a handshake protocol controls the rate of test data flow between the automatic test equipment (ATE) and device under test (DUT). The test time reduction accomplished depends upon an average activity factor α. For low α, about 50% test time reduction is analytically shown. With moderate activity, α = 0.5, simulated test data gives about 25% test time reduction for ITC02 benchmarks. For full scan s38584, the dynamic scan clock control reduced the test time by 19% when fully specified ATPG vectors were used and by 43% for vectors with don't cares. BIST with dynamic clock showed about 19% test time reduction for the largest ISCAS89 circuits in which the hardware activity monitor and scan clock control required about 2-3% hardware overhead.

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock

“…We propose techniques to reduce test time in externally tested scan circuits through dynamic control of scan clock frequency for which peak activity factor may or may not be pre-computed. The test time reduction achieved is better than those of prior proposals [6], [7].…”

“…Scan-in bits are monitored and allow speed up of clock. Implementations of such a scheme for external test [6] and for self-test [7] may be found in recent papers.…”

“…A recent proposal [6], [7] suggests dynamic control of scan clock frequency in both self test and externally tested scan circuits. It is assumed that the circuit activity is proportional to the activity in the scan register.…”

A Test Time Theorem and its Applications

“…We can continue to reduce the voltage as long as the operation is power constrained. Once T structure exceeds T power , the operation becomes structure constrained and according to Equation (6), T test starts increasing. T test attains its minimum value at supply voltage for which T power = T structure .…”

ATE test time reduction using asynchronous clock period

“…Shanmugasundaram and Agrawal [25] [26] proposed a technique to reduce the test time in power constrained built in self test (BIST) circuits. They implement an activity monitor that increases the clock frequency if the monitor records low activity in the chain, otherwise it decreases the frequency.…”