Dynamic scan clock control in BIST circuits

Abstract

Abstract-We dynamically monitor per cycle scan activity to speed up the scan clock for low activity cycles without exceeding the specified peak power budget. The activity monitor is implemented as on-chip hardware. Two models, one for test sets with peak activity factor of 1 and the other for test sets with peak activity factor lower than 1 have been proposed. In test sets with peak activity factors of 1, the test time reduction accomplished depends upon an average activity factor of αin. For low αin, about 50% test time reduction is analytically shown. With moderate activity, αin = 0.5, simulated test data gives about 25% test time reduction for ITC02 benchmarks. BIST with dynamic clock showed about 19% test time reduction for the largest ISCAS89 circuits in which the hardware activity monitor and scan clock control required about 2-3% hardware overhead. In test sets with peak activity factors lower than 1, the test time reduction depends on an input activity factor of αin and an output activity factor of αout. For low αin and high αout, a test time reduction of about 50% is analytically shown.

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock

“…We propose techniques to reduce test time in externally tested scan circuits through dynamic control of scan clock frequency for which peak activity factor may or may not be pre-computed. The test time reduction achieved is better than those of prior proposals [6], [7].…”

“…Scan-in bits are monitored and allow speed up of clock. Implementations of such a scheme for external test [6] and for self-test [7] may be found in recent papers.…”

“…Given a value of the peak scan chain activity α peak due to captured values, the slowest scan clock frequency is given by [5]- [7]:…”

“…A recent proposal [6], [7] suggests dynamic control of scan clock frequency in both self test and externally tested scan circuits. It is assumed that the circuit activity is proportional to the activity in the scan register.…”

Dynamic scan clock control for test time reduction maintaining peak power limit

“…Reference [16] proposes a strategy to identify flip-flops to be removed from scan chains to increase the observability of the circuit so that faults activated during scan cycles can be observed at a primary output. The original technique of this paper whose details and some implementations are reported in recent documents [17], [18] can be additionally applied to any scan circuit that may include other methods mentioned above.…”