Dynamic scheduling of voter checks in FPGA-based TMR systems

Nguyen, Nguyen T. H.; Agiakatsikas, Dimitris; Cetin, Ediz; Diessel, Oliver

doi:10.1109/fpt.2016.7929525

Cited by 7 publications

(11 citation statements)

References 7 publications

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“…Table 5 tabulates the MTTD errors using the round-robin, VSE and VRVC approaches as well as the percentage reduction from round robin to VSE and VRVC when the RC is operated at different clock frequencies. The MTTDs are calculated using (8) with the number of checks listed in Table 2, and in [10], together with the average number of errors per component, as tabulated in Table 4.…”

Section: Fault Injection Resultsmentioning

confidence: 99%

“…A number of publications report on techniques that have been developed to decrease the MTTD and correct configuration memory errors in FPGA-based systems with a view to improve system reliability. These techniques are based either on TMR-MER [6,9,10,[16][17][18] or on scrubbing [19][20][21][22][23].…”

Section: Related Workmentioning

confidence: 99%

“…For each simulation, the size of each triplicated module, as measured in number of essential bits, was chosen randomly in a range from 10,000 to 2,000,000 bits using one of three size distributions: uniform, quadratic and exponential. For a given number of system components (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20) and at each orbit level (LEO and GEO), we evaluated the performance of each schedule (VRVC, round robin, VSE) over five trials for each module size distribution (uniform, quadratic and exponential). Please note that there is no difference in hardware cost between VRVC and RR as both are controlled by a programmable RC.…”

Section: Assumptions and Implementationsmentioning

confidence: 99%

“…Simulation experiments were carried out to assess the performance of the proposed VRVC schedule relative to both round‐robin voter checking and the dynamically determined VSE approach presented in [10]. These experiments involved simulating FPGA‐based systems comprising sets of TMR components and assessing the MTTF for each voter checking method at low‐ and high‐radiation orbits.…”

Section: Evaluation – Synthetic Problemsmentioning

confidence: 99%

“…In [10], we proposed an on‐chip voter scheduling engine (VSE) to help the RC dynamically adjust the order in which RRs from TMR voters are checked based on the likelihood of the next component that is checked being in error. The approach was implemented based on the idea that the RRs from the more vulnerable components, i.e.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Scheduling configuration memory error checks to improve the reliability of FPGA‐based systems

Nguyen

Cetin²,

Diessel³

2018

IET Computers & Digital Techniques

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Field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR-MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15-23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin. Nomenclature Symbol Definition N number of TMR components in the system Ck component k, k = 1, …, N O kn Ck is observed for the nth time by checking its voter(s) Δt o time period between successive voter observations (assumed to be constant for a given system setting) Δt dk time period between two consecutive observations of Ck Δt rk time period to recover a faulty module of Ck Δt k total time period over which Ck can fail Δt di j time period between successive observations of Ci and Cj Δt d′i j average time period between two consecutive observations of Ci in the interval between two consecutive observations of Cj IET Comput. Digit. Tech.

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Section: Fault Injection Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Assumptions and Implementationsmentioning

confidence: 99%

Section: Evaluation – Synthetic Problemsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Scheduling configuration memory error checks to improve the reliability of FPGA‐based systems

Nguyen

Cetin²,

Diessel³

2018

IET Computers & Digital Techniques

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DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs

Jiang

et al. 2020

2020 57th ACM/IEEE Design Automation Conference (DAC)

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Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems

Nguyen

Cetin

Diessel

2017

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). A common technique for dealing with SEUs is Triple Modular Redundancy (TMR) combined with Module-based configuration memory Error Recovery (MER). By triplicating components and voting on their outputs, TMR helps localize the configuration memory errors, and by reconfiguring the faulty component, MER swiftly corrects the errors. However, the order in which the voters of TMR components are checked has an inevitable impact on the overall system reliability. In this paper, we outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. Using the derived reliability models we demonstrate that the reliability of an exemplar system is improved by up to 29% when the critical components are checked more frequently for the presence of configuration memory errors than when they are checked in round-robin order or by up to 11% when the next component to be checked is chosen at run time based on the likelihood that it has failed.

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Dynamic scheduling of voter checks in FPGA-based TMR systems

Cited by 7 publications

References 7 publications

Scheduling configuration memory error checks to improve the reliability of FPGA‐based systems

Scheduling configuration memory error checks to improve the reliability of FPGA‐based systems

DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs

Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems

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