Dynamic Task Scheduling on Multicore Automotive ECUs

Abstract

Automobile manufacturers are controlled by stringent govt. regulations for safety and fuel emissions and motivated towards adding more advanced features and sophisticated applications to the existing electronic system. Ever increasing customer's demands for high level of comfort also necessitate providing even more sophistication in vehicle electronics system. All these, directly make the vehicle software system more complex and computationally more intensive. In turn, this demands very high computational capability of the microprocessor used in electronic control unit (ECU). In this regard, multicore processors have already been implemented in some of the task rigorous ECUs like, power train, image processing and infotainment. To achieve greater performance from these multicore processors, parallelized ECU software needs to be efficiently scheduled by the underlaying operating system for execution to utilize all the computational cores to the maximum extent possible and meet the real time constraint. In this paper, we propose a dynamic task scheduler for multicore engine control ECU that provides maximum CPU utilization, minimized preemption overhead, minimum average waiting time and all the tasks meet their real time deadlines while compared to the static priority scheduling suggested by Automotive Open Systems Architecture (AUTOSAR).

Performance optimization of task intensive real time applications on multicore ECUs - a hybrid scheduler

“…According to Automotive Open System Architecture (AUTOSAR) 4.0, there are certain limitations on multicore software implementation. The scheduling algorithms strictly partition the tasks based on similar functionality or periodicity or dependency and assign those tasks to fixed cores [10,11]. Tasks are scheduled in the intended core based on their statically assigned priority.…”

A Mixed Approach Scheduling Algorithm for Multicore Automotive ECUs at Contingency Conditions

“…The implementation of multiple cores incurs greater design complexity both for hardware and software. Applications running on different cores need to have efficient interprocess communication (IPC) mechanisms, shared-memory data structures, appropriate synchronization mechanism and primitives for shared resources protection [9].…”