Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

Swift, G.M.; Rezgui, S.; George, J.; Carmichael, C.; Napier, Mary E.; Maksymowicz, J.; Moore, Jason; Lesea, A.; Koga, R.; Wrobel, T. F.

doi:10.1109/tns.2004.839190

Cited by 41 publications

(24 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The novel approach, here proposed for fast detecting and correcting SEU-induced configuration errors, exploits the internal dynamic partial readback and reconfiguration capabilities introduced in the XILINX Virtex FPGA families, extensively employed in numerous space missions [12][13]. Error Detection And Correction (EDAC) Hamming Codes [14] of the configuration bitstream are precomputed by an on purpose software, and then stored in a TMR-ed reference memory inside the SFPGA during its first configuration.…”

Section: Fig 1 Traditional Rhdb Methodologies; (A) the Tmr Solutionmentioning

confidence: 99%

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

Lanuzza

Zicari

Frustaci

et al. 2009

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. This paper presents an efficient approach to protect an FPGA design against Single Event Upsets (SEUs). A novel configuration scrubbing core, instantiated at the top level of the user project, is used for internal detection and correction of SEU-induced configuration errors without requiring further external radiation hardened control hardware. As demonstrated in the paper, this approach combines the benefits of fast SEU faults detection with fast restoration of the device functionality and small overhead. Moreover, the proposed technique result highly versatile and can be adopted for different FPGA device families.

show abstract

Section: Fig 1 Traditional Rhdb Methodologies; (A) the Tmr Solutionmentioning

confidence: 99%

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

Lanuzza

Zicari

Frustaci

et al. 2009

Lecture Notes in Computer Science

View full text Add to dashboard Cite

show abstract

“…There is a plethora of radiation-based methods which use accelerated radiation testing to measure the sensitivity of FPGA devices to SEUs [7]- [9], [11], [19], [36]. In these approaches, a prototype of the system under study is exposed to a flux of radiation, originated either by radioactive sources or by particle accelerators.…”

Section: Previous Workmentioning

confidence: 99%

Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

Asadi¹,

Tahoori

Mullins³

et al. 2007

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

Abstract-Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, single event upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design.In this paper we analyze the soft error vulnerability of FPGAs used in information systems. Since the reliability requirements of these high performance information subsystems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in overall system reliability. We present an analytical approach (versus fault injection) for soft error rate estimation in FPGA-based designs. We also validate the projections produced by our analytical model using field error rates obtained from failure data obtained from a large FPGA-based design used in the Logical Unit Module board of a commercial information system. This comparison confirms that the projections obtained from our analytical tool are accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied).Index Terms-Error analysis, field programmable gate arrays (FPGA), information systems, logic circuit fault tolerance, reliability estimation, reliability modeling, SRAM chips (SRAM-based FPGAs).

show abstract

“…The greatest advantage of these methods is the higher controllability of the experiments, in contrast to the unpredictability of radiation injection, which enables a better diagnostic of the effects of each SEU. A combination of both techniques, not only to increase the controllability of the experiments, but also to verify the accuracy of the emulation fault injection techniques used, may be found in [4,5,12,13].…”

Section: Overview Of Published Data About Radiationmentioning

confidence: 99%

“…After extensive testing, several authors proved that SEU-induced failures can be properly controlled for the Virtex family of FPGA devices using TMR [6,7,9,13,17]. Fault tolerance is achieved using extra components to instantaneously mask the effect of a faulty component, meaning that no fault propagation will occur.…”

Section: Overview Of Published Data About Radiationmentioning

confidence: 99%

A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs

Gericota¹,

Lemos²,

Alves³

et al. 2007

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

View full text Add to dashboard Cite

-To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults.Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of Multi-Bit Upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established.A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.

show abstract

Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

Cited by 41 publications

References 6 publications

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs

Contact Info

Product

Resources

About