An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

Abstract

Abstract. This paper presents an efficient approach to protect an FPGA design against Single Event Upsets (SEUs). A novel configuration scrubbing core, instantiated at the top level of the user project, is used for internal detection and correction of SEU-induced configuration errors without requiring further external radiation hardened control hardware. As demonstrated in the paper, this approach combines the benefits of fast SEU faults detection with fast restoration of the device functionality and small overhead. Moreover, the proposed technique result highly versatile and can be adopted for different FPGA device families.

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications

“…In this way, the amount and the complexity of external controlling hardware is strongly limited with respect to SEU mitigation solutions based on the external reconfiguration [Carmichael et al 2000;Gokhale et al 2006]. This work extends the SEU mitigation system presented in our previous paper [Lanuzza et al 2009] by increasing its potentialities in sensitive way. The following distinguishing and novel features are actually introduce.…”

“…In this way, differently from Carmichael and Tseng [2008], Heiner et al [2008], and Lanuzza et al [2009] also MBUs can be opportunely mitigated. This is a very important property, which can significantly improve the reliability of highly scaled FPGA-based designs when used in harsh radiation environments.…”

“…Moreover, starting from the Virtex-II series, Xilinx also provides an Internal Configuration Access Port (ICAP) [Xilinx 2007] that, as demonstrated in Carmichael and Tseng [2008], in Heiner et al [2008] and in our previous work [Lanuzza et al 2009], can be used to support a self-hosting configuration management system with the purpose of mitigating radiation effects. In this way, the amount and the complexity of external controlling hardware is strongly limited with respect to SEU mitigation solutions based on the external reconfiguration [Carmichael et al 2000;Gokhale et al 2006].…”

“…As described in the following, this simple approach can potentially reduce memory requirements up to the 50% with respect to Lanuzza et al [2009]. (3) Different experimental and analytical analyses have been performed to evaluate the effectiveness of the proposed approach.…”

Design and analysis of efficient synthesis algorithms for EDAC functions in FPGAs

“…Emails: carlos.colodro@upct.es, rafael.toledo@upct.es SRAM-based FPGAs are specially sensitive to radiation because of the fact that the configuration memory that defines the circuitry implemented inside them is vulnerable to SEUs. Regarding this matter, Hamming EDAC (Error Detection And Correction) cores with SEC-DED (Single-Error-Correction, Double-Error-Detection) capabilities have proven to be an effective way to protect the internal configuration memory [1], [17], [25], [29], [30], as well as other external volatile memories [6], [23], [24]. However, the fact of such cores being placed inside the FPGA makes them less reliable, as they can also be affected by SEUs in configuration memory.…”