Dynamic thermal clock skew compensation using tunable delay buffers

Chakraborty, Anirban; Duraisami, K.; Sathanur, Ashoka; Sithambaram, P.; Benini, Luca; Macii, Alberto; Macii, Enrico; Poncino, Massimo

doi:10.1145/1165573.1165612

Cited by 20 publications

(10 citation statements)

References 35 publications

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“…Recently, post-silicon tuning capability has been introduced to clock tree design to remove unintentional skews and boost timing yield under increasing process variations [8]. A representative example is Intel's dual-core Itanium processor, which places tunable delay buffers (TDBs) in the clock distribution network to cancel clock skew variations [9].…”

Section: Post-silicon Clock Skew Tuningmentioning

confidence: 99%

“…Earlier works in this domain [1][2][3][4][5] try to find a good clock schedule that maximizes the timing slack of all paths. Recently, with the introduction of tunable clock tree to combat process variation [9], researchers have also presented various post-silicon clock skew tuning techniques to improve circuit timing performance [6,8,[10][11][12].…”

Section: Introductionmentioning

confidence: 99%

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Online clock skew tuning for timing speculation

Ye¹,

Yuan²,

Xu³

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Section: Post-silicon Clock Skew Tuningmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Online clock skew tuning for timing speculation

Ye¹,

Yuan²,

Xu³

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Chakraborty et al considered the problem of guaranteeing the timing correctness of sequential circuits under on-chip temperature variation. The idea is to insert tuneable delay buffers into the clock tree, which can be adjusted on-the-fly [6,7]. Long et al [8] solved the same problem by introducing SACTA, a selfadjusting clock tree architecture leveraging the specially designed skew buffers to achieve adaptability.…”

Section: Related Workmentioning

confidence: 99%

Automated design of self-adjusting pipelines

Long

Memik

2008

Proceedings of the 45th Annual Design Automation Conference

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We propose a self-adjusting pipeline structure to enhance chip performance and robustness considering the effects of process variations. We achieve this by introducing delay sensors to monitor internal timing violations within a pipeline stage and variable clock skew buffers to adjust the timing of the pipeline stage based on the feedback from the delay sensors. Furthermore, we formulate the delay sensor insertion and variable clock skew configuration problem as a stochastic mixed-integer programming problem and propose a simulated-annealing based algorithm to solve it. A comparison between the designs with and without the self-adjusting enhancement reveals that, we are able to improve the average performance of a batch of chips by 9.5%.

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“…The methods discussed above are applied as pre-silicon optimization or post-silicon adjustment before shipping the chips to customers. Recently, further advances have been made to apply the clock tuning elements on-line to improve the lifetime performance [20]- [23]. The method in [21] adjusts the clock skews during runtime according to the occurrence of timing errors to achieve much better performance in timingspeculative circuits.…”

Section: Introductionmentioning

confidence: 99%

Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements

Schlichtmann

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Post-silicon clock tuning elements are widely used in high-performance designs to mitigate the effects of process variations and aging. Located on clock paths to flip-flops, these tuning elements can be configured through the scan chain so that clock skews to these flip-flops can be adjusted after manufacturing. Owing to the delay compensation across consecutive register stages enabled by the clock tuning elements, higher yield and enhanced robustness can be achieved. These benefits are, nonetheless, attained by increasing die area due to the inserted clock tuning elements. For balancing performance improvement and area cost, an efficient timing analysis algorithm is needed to evaluate the performance of such a circuit. So far this evaluation is only possible by Monte Carlo simulation which is very timingconsuming. In this paper, we propose an alternative method using graph transformation, which computes a parametric minimum clock period and is more than 10 4 times faster than Monte Carlo simulation while maintaining a good accuracy. This method also identifies the gates that are critical to circuit performance, so that a fast analysis-optimization flow becomes possible.

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Dynamic thermal clock skew compensation using tunable delay buffers

Cited by 20 publications

References 35 publications

Online clock skew tuning for timing speculation

Online clock skew tuning for timing speculation

Automated design of self-adjusting pipelines

Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements

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