Online clock skew tuning for timing speculation

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

et al. 2013

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With technology scaling, integrated circuits suffer from increasingly severe static and dynamic variations, which often manifest themselves as infrequent timing errors on circuit speed paths, if a large timing guard-band is not reserved. This paper presents a new forward timing error correction scheme, namely ForTER, which predicts whether the occurrence of timing errors would propagate to the next level of sequential elements and corrects them without necessarily borrowing timing slack. The proposed technique can be combined with other timing error resilient circuit design techniques to further improve circuit performance, as demonstrated in our experimental results with various benchmark circuits.

Section: Results On Timing-speculative Circuitsmentioning

confidence: 99%

“…Such huge benefits have motivated a large amount of recent research efforts on design and optimization techniques for timing-speculative circuits (e.g., [6][7][8][9][10][11][12]). …”

Section: Related Workmentioning

confidence: 99%

ForTER: A forward error correction scheme for timing error resilience

Zhang

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

et al. 2013

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“…Their measurement results show that the resilient design enables 25% throughput gain over a conventional design by eliminating the guardband from circuit dynamic variations and an additional 7% throughput increase from exploiting the path-activation probabilities for timing error rate reduction. The above benefits have motivated a large amount of recent research efforts on design and optimization techniques for timing-speculative circuits (e.g., [16][17][18][19]). …”

Section: Timing Speculationmentioning

confidence: 99%

Post-placement voltage island generation for timing-speculative circuits

Proceedings of the 50th Annual Design Automation Conference

Sun

et al. 2013

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Region-based multi-supply voltage (MSV) design, by which circuits are partitioned into multiple "voltage islands" and each island operates at a supply voltage that meets its own performance requirement, is an effective technique to tradeoff power and performance. Different from conventional voltage island generation techniques that work in a conservative manner to guarantee "always correct" computation, in this work, we investigate the MSV design problem for timingspeculative circuits, which achieves high energy-efficiency by allowing the occurrence of infrequent timing errors and correcting them online. A novel algorithm based on dynamic programming is developed to tackle this problem. Experimental results on various benchmark circuits demonstrate the effectiveness of the proposed methodology.

“…Recently, Intel [7] has demonstrated in their test chip that a timing-speculative microprocessor is able to achieve more than 30% throughput gain when compared to a conventional microprocessor design under the same supply voltage. The above benefits have motivated a large amount of recent research efforts on design and optimization techniques for timing-speculative circuits (e.g., [8][9][10][11]). …”

Section: Introductionmentioning

confidence: 99%

On testing timing-speculative circuits

Proceedings of the 50th Annual Design Automation Conference

Liu

Jone

et al. 2013

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By allowing the occurrence of infrequent timing errors and correcting them online, circuit-level timing speculation is one of the most promising variation-tolerant design techniques. How to effectively test timingspeculative circuits, however, has not been addressed in the literature. This is a challenging problem because conventional scan techniques cannot provide sufficient controllability and observability for such circuits. In this paper, we propose novel techniques to achieve high fault coverage for timing-speculative circuits without incurring high designfor-testability cost. Experimental results on various benchmark circuits demonstrate the effectiveness of the proposed solution.