Dynamic thermal management using thin-film thermoelectric cooling

Chaparro, Pedro; González, José María Faci; Cai, Quan; Chrysler, G.

doi:10.1145/1594233.1594258

Cited by 13 publications

(8 citation statements)

References 18 publications

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“…Long et al propose a system-level design to optimize bias current and placement of on-package TECs based on application of greedy algorithms and a modified compact thermal models of the TEC interfaces [4]. Chaparro et al examine on-die thermal management techniques such as Dynamic Frequency and Voltage Scaling (DVFS) [5]. Sri Choday et al describe methodologies for optimization of material properties of TE devices to augment their cooling properties [6].…”

Section: Related Workmentioning

confidence: 99%

Systemic optimization of on-chip thermoelectric cooling

Rangarajan

Karnik

Khanna

et al. 2015

2015 IEEE CPMT Symposium Japan (ICSJ)

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Economic viability of on-package, in-situ cooling based on Thin-film Thermoelectric Coolants (TF-TEC) for hotspot cooling involves myriad challenges necessitating engineering trade-offs. Principal factors include the cost of integration, the net energy consumption of the TEC based system, as well as systemlevel complexities arising from issues such as mutual thermal conflicts and interdependencies between the TEC and other package-level entities such as the Thermal grease (TIM), impact on the external convective cooling system, and the number of hotspots present. In this paper, we examine these challenges both analytically and empirically, and propose a heuristic based method to overcome them. The method forms the basis for a generic optimization framework that enables system-level optimization of on-chip thermoelectric cooling in a commercial microprocessor package. We find a resultant cooling of up to 3°C at TDP delivered per core with a ~11% improvement in energy efficiency.

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Section: Related Workmentioning

confidence: 99%

Systemic optimization of on-chip thermoelectric cooling

Rangarajan

Karnik

Khanna

et al. 2015

2015 IEEE CPMT Symposium Japan (ICSJ)

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“…A TE Cooler (TEC) operates on the basis of the Peltier effect that helps to reduce the junction temperature by dumping heat from the cold side to the hot side when a current flows through it [1][2][3][4][5][6]. The integration of Bi 2 Te 3 based thin film super-lattice TECs within microprocessor package has been experimentally demonstrated [2].…”

Section: Introductionmentioning

confidence: 99%

“…The design and run-time approaches for integration of TEC are also being explored. Long et al have explored algorithms for optimal placements of TECs in a chip to maximize the cooling efficiency [3,4]. The applications of TECs in dynamic thermal management of microprocessors have been studied [5,6].…”

Section: Introductionmentioning

confidence: 99%

Energy efficient active cooling of integrated circuits using autonomous Peltier/Seebeck mode switching of a thermoelectric module

Parthasarathy

Ahmed

Alexandrov

et al. 2014

2014 Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)

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Thermoelectric (TE) devices have shown promise for ondemand cooling of ICs. However, the additional energy required for cooling remains a challenge for the successful deployment of these devices. This paper presents a closed loop control system that dynamically switches a TE module between Peltier and Seebeck modes depending on chip temperature. The autonomous system harvests energy during regular operation and uses the harvested energy to cool during high power operation. The system is demonstrated using a commercial thin-film TE device, an integrated boost regulator and few off chip components. The feasibility of the integration of the TEM and the automated mode switching within the microprocessor package is also evaluated.

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“…TE modules made of miniaturized bulk Bi 2 Te 3 were also studied for dynamic thermal management in a multicore chip where one or more cores were augmented with TE devices to increase their performance [4]. Simulation studies showed that a 16-core processor could achieve performance that was within 8% of a thermally unconstrained processor [4] when multiple TE devices are placed on the die.…”

mentioning

confidence: 99%

“…Simulation studies showed that a 16-core processor could achieve performance that was within 8% of a thermally unconstrained processor [4] when multiple TE devices are placed on the die. Hence, TE devices are also promising for chip performance enhancement.…”

mentioning

confidence: 99%

Prospects of Thin-Film Thermoelectric Devices for Hot-Spot Cooling and On-Chip Energy Harvesting

Choday

Lundstrom

Roy

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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Advances in thin-film thermoelectric (TE) materials have created opportunities for using TE devices in high heat flux applications such as hot-spot (H-S) cooling and on-chip energy harvesting. In this paper, we compare the performance of TE modules integrated directly on the silicon die with those that are attached to the heat spreader of the chip package. We make use of the Bi 2 Te 3 /Sb 2 Te 3 super lattice material to explore tradeoffs between the two integration options for H-S cooling and energyharvesting applications. Package level finite element simulations show that on-chip energy harvesting can yield up to 30 mW of power from an H-S with a heat flux of 200 W/cm 2 , or the same H-S can be cooled as much as 19°C in the cooling mode. In addition, the TE module integrated on the die is shown to have a disadvantage due to the higher thermal resistance from the hot side of the module to the ambient.

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Dynamic thermal management using thin-film thermoelectric cooling

Cited by 13 publications

References 18 publications

Systemic optimization of on-chip thermoelectric cooling

Systemic optimization of on-chip thermoelectric cooling

Energy efficient active cooling of integrated circuits using autonomous Peltier/Seebeck mode switching of a thermoelectric module

Prospects of Thin-Film Thermoelectric Devices for Hot-Spot Cooling and On-Chip Energy Harvesting

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