Dynamic voltage &amp; frequency scaling with online slack measurement

Levine, Joshua M.; Stott, Edward; Cheung, Peter Y. K.

doi:10.1145/2554688.2554784

Cited by 38 publications

(28 citation statements)

References 10 publications

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“…In this paper, the framework is extended with new tools and IP components to support the latest generation Zynq Ultrascale devices fabricated in 16 nm and a comparison is performed with the older 28 nm devices in terms of energy adaptivity and performance for the BNN application. Related to this research is the FPGA-focused voltage and frequency scaling work done in [19] which uses an online slack measurement (OSM) technique. The OSM method uses direct timing measurement of the application circuit to respond to variation, temperature, and degradation.…”

Section: Adaptive Voltage and Frequency Scalingmentioning

confidence: 99%

Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling

Nunez-Yanez

2019

IEEE Trans. Comput.

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This research presents the extension and application of a voltage and frequency scaling framework called Elongate to a high-performance and reconfigurable binarized neural network. The neural network is created in the FPGA reconfigurable fabric and coupled to a multiprocessor host that controls the operational point to obtain energy proportionality. Elongate instruments a design netlist by inserting timing detectors to enable the exploitation of the operating margins of a device reliably. The elongated neural network is re-targeted to devices with different nominal operating voltages and fabricated with 28 nm (i.e., Zynq) and 16nm (i.e., Zynq Ultrascale) feature sizes showing the portability of the framework to advanced process nodes. New hardware and software components are created to support the 16nm fabric microarchitecture and a comparison in terms of power, energy and performance with the older 28 nm process is performed. The results show that Elongate can obtain new performance and energy points that are up to 86 percent better than nominal at the same level of classification accuracy. Trade-offs between energy and performance are also possible with a large dynamic range of valid working points available. The results also indicate that the built-in neural network robustness allows operation beyond the first point of error while maintaining the classification accuracy largely unaffected.Index Terms-energy efficiency, convolutional neural network, DVFS, FPGA Ç The author is with the

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Section: Adaptive Voltage and Frequency Scalingmentioning

confidence: 99%

Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling

Nunez-Yanez

2019

IEEE Trans. Comput.

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“…However, the inaccuracy of path monitor circuitries in FPGAs and even ASICs has been well elaborated [24], [25], [26], [27]. Levine et al employ timing error detectors inserted as capture registers with a phase-shifted clock at the end of critical paths to find out the timing slack of FPGA-mapped designs through a gradual reduction of voltage [24]. Their approach adds extra area and power overhead, cannot be implemented in paths heading to hard blocks such as memories, and assumes the corresponding paths will be exercised at runtime.…”

Section: Related Workmentioning

confidence: 99%

Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms

Salamat

Khaleghi

Imani

et al. 2019

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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The continuous growth of big data applications with high computational and scalability demands has resulted in increasing popularity of cloud computing. Optimizing the performance and power consumption of cloud resources is therefore crucial to relieve the costs of data centers. In recent years, multi-FPGA platforms have gained traction in data centers as lowcost yet high-performance solutions particularly as acceleration engines, thanks to the high degree of parallelism they provide. Nonetheless, the size of data centers workloads varies during service time, leading to significant underutilization of computing resources while consuming a large amount of power, which turns out as a key factor of data center inefficiency, regardless of the underlying hardware structure. In this paper, we propose an efficient framework to throttle the power consumption of multi-FPGA platforms by dynamically scaling the voltage and hereby frequency during runtime according to prediction of, and adjustment to the workload level, while maintaining the desired Quality of Service (QoS). This is in contrast to, and more efficient than, conventional approaches that merely scale (i.e., power-gate) the computing nodes or frequency. The proposed framework carefully exploits a pre-characterized library of delay-voltage, and power-voltage information of FPGA resources, which we show is indispensable to obtain the efficient operating point due to the different sensitivity of resources w.r.t. voltage scaling, particularly considering multiple power rails residing in these devices. Our evaluations by implementing state-of-the-art deep neural network accelerators revealed that, providing an average power reduction of 4.0×, the proposed framework surpasses the previous works by 33.6% (up to 83%).

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“…Thus d worst is the target delay that our algorithm attempts to deliver with lower voltages. One drawback of previous voltage scaling approaches [14], [16] is they invade this reliability margin when they speculatively reduce the voltage until observing an error in the output, as the error does not show up in regular conditions. The core of the algorithm is a loop where, based on previously obtained temperature for each tile (set to T amb initially), it finds the (V core , V bram ) pair that minimizes the power while watches over the delay of candidate pair to not exceed d worst .…”

Section: B Proposed Thermal-aware Voltage Scaling Flowmentioning

confidence: 99%

FPGA Energy Efficiency by Leveraging Thermal Margin

Khaleghi

Salamat

Imani

et al. 2019

2019 IEEE 37th International Conference on Computer Design (ICCD)

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FPGA devices are continuously evolving to meet high computation and performance demand for emerging applications. As a result, cutting edge FPGAs are not energy efficient as conventionally presumed to be, and therefore, aggressive power-saving techniques have become imperative. The clock rate of an FPGA-mapped design is set based on worst-case conditions to ensure reliable operation under all circumstances. This usually leaves a considerable timing margin that can be exploited to reduce power consumption by scaling voltage without lowering clock frequency. There are hurdles for such opportunistic voltage scaling in FPGAs because (a) critical paths change with designs, making timing evaluation difficult as voltage changes, (b) each FPGA resource has particular power-delay trade-off with voltage, (c) data corruption of configuration cells and memory blocks further hampers voltage scaling. In this paper, we propose a systematical approach to leverage the available thermal headroom of FPGA-mapped designs for power and energy improvement. By comprehensively analyzing the timing and power consumption of FPGA building blocks under varying temperatures and voltages, we propose a thermal-aware voltage scaling flow that effectively utilizes the thermal margin to reduce power consumption without degrading performance. We show the proposed flow can be employed for energy optimization as well, whereby power consumption and delay are compromised to accomplish the tasks with minimum energy. Lastly, we propose a simulation framework to be able to examine the efficiency of the proposed method for other applications that are inherently tolerant to a certain amount of error, granting further power saving opportunity. Experimental results over a set of industrial benchmarks indicate up to 36% power reduction with the same performance, and 66% total energy saving when energy is the optimization target.

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Dynamic voltage & frequency scaling with online slack measurement

Cited by 38 publications

References 10 publications

Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling

Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling

Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms

FPGA Energy Efficiency by Leveraging Thermal Margin

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