Dynamic write-level and read-level signal design for MLC NAND flash memory

Abstract

In this paper, we propose dynamic write-level and read-level voltage scheme for MLC NAND flash memory. We study the characteristics of flash channel which can be modeled as mixture of Uniform and Exponential distribution. Since this channel shows non-stationary behavior , we present probability of error analysis and introduce the concept of dynamically adjusting the verify-level (write-level) and quantization-level (readlevel) voltage values over varying flash channel. The proposed dynamic voltage based method outperforms fixed verify-level voltage scheme. We demonstrate improvements in bit-error-rate (BER) performance and cell storage capacity for the proposed signal design scheme.

A polynomial based valley search algorithm for 3D NAND flash memory

“…Valley search is a solution to find the optimal read voltage (OPT), not only satisfy the verification of ECC as read retry, but also makes the read error minimum. At present, many schemes have been developed such as [5,6,7,8,9,10,11]. A typical method is V T tracking read proposed by Toshiba [12], which requires searching for at least one threshold voltage distribution state, however, it may require many times of reading and low efficiency.…”

Coding and signal processing for NAND flash memory

“…In [63], In the conventional MLC flash technology, to avoid the effect of voltage overshoot errors, the cell's threshold voltage is configured on desired write voltage levels in multiple rounds of programming. In [66][67][68], for both MLC and rank modulation schemes, the optimal programming step size has been investigated, keeping the number of programming rounds constant and assuming fixed write voltage levels.…”