Dynamically changeable secure scan architecture against scan-based side channel attack

Atobe, Yuta; Shi, Youhua; Yanagisawa, Masao; Togawa, Nozomu

doi:10.1109/isocc.2012.6407063

Cited by 33 publications

(20 citation statements)

References 6 publications

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“…As a result, countermeasures for scan attacks are no longer secure in the more generous threat model. Certain scan attack countermeasures rely on scan chain authentication [14], [30], [31], [32]. These countermeasures can be circumvented by having access to a reverse-engineered netlist, as the on-chip logic that implements secure scan can also be reverse-engineered to bypass authentication.…”

Section: Scansat Versus Scan Attacksmentioning

confidence: 99%

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ScanSAT: Unlocking Static and Dynamic Scan Obfuscation

Alrahis

Yasin

Limaye

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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While financially advantageous, outsourcing key steps, such as testing, to potentially untrusted Outsourced Assembly and Test (OSAT) companies may pose a risk of compromising on-chip assets. Obfuscation of scan chains is a technique that hides the actual scan data from the untrusted testers; logic inserted between the scan cells, driven by a secret key, hides the transformation functions that map the scan-in stimulus (scan-out response) and the delivered scan pattern (captured response). While static scan obfuscation utilizes the same secret key, and thus, the same secret transformation functions throughout the lifetime of the chip, dynamic scan obfuscation updates the key periodically. In this paper, we propose ScanSAT: an attack that transforms a scan obfuscated circuit to its logic-locked version and applies the Boolean satisfiability (SAT) based attack, thereby extracting the secret key. We implement our attack, apply on representative scan obfuscation techniques, and show that ScanSAT can break both static and dynamic scan obfuscation schemes with 100% success rate. Moreover, ScanSAT is effective even for large key sizes and in the presence of scan compression.

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Section: Scansat Versus Scan Attacksmentioning

confidence: 99%

“…Scan obfuscation/masking defenses Scan chain authentication[30],[31], State dependent scan flip-flop based scan (SDSFF)[32] RE-vulnerable Flipped scan[39], XOR scan[40], double feedback XOR scan[41] RE-vulnerable…”

mentioning

confidence: 99%

ScanSAT: Unlocking Static and Dynamic Scan Obfuscation

Alrahis

Yasin

Limaye

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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“…In [45], the scan patterns/responses are decrypted/encrypted at each scan input/output, respectively, which is conducted by highly efficient and secure block cipher at each scan port. But these countermeasures are defeated by resetting attack [46] and flushing attack [47]. By resetting the scan cells or flushing the scan chain with the known patterns, the fixed inverted bits [46] and modified bits [47] in the obfuscated scan chain can be identified so that the plaintext can be deciphered.…”

Section: Vulnerabilities Of the Dftmentioning

confidence: 99%

“…DIPs rule out incorrect keys utilizing the output corruptibility of the miter circuit constructed using locked design and activated design. For sequential designs, it is assumed that an IC's internal states can be accessed and controlled via scan chains to [59] Internal States Scan encryption [45], DOS [51] Resetting Attack [46] Internal Secrets LCSS [48], DOS [51], Lock & Key [60], Scan encryption [45] Flushing Attack [47] Bit-role Identification Combinational Function Recovery [54] Functionality DOS [51] SAT Attack [4] Obfuscation Key…”

Section: Vulnerabilities Of the Dftmentioning

confidence: 99%

Defense-in-depth: A recipe for logic locking to prevail

Rahman

Wang

et al. 2020

Integration

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Logic locking has emerged as a promising solution for protecting the semiconductor intellectual Property (IP) from the untrusted entities in the design and fabrication process. Logic locking hides the functionality of the IP by embedding additional key-gates in the circuit. The correct output of the chip is produced, once the correct key value is available at the input of the key-gates. The confidentiality of the key is imperative for the security of the locked IP as it stands as the lone barrier against IP infringement. Therefore, the logic locking is considered as a broken scheme once the key value is exposed. The research community has shown the vulnerability of the logic locking techniques against different classes of attacks, such as Oracle-guided and physical attacks. Although several countermeasures have already been proposed against such attacks, none of them is simultaneously impeccable against Oracle-guided, Oracle-less, and physical attacks. Under such circumstances, a defense-in-depth approach can be considered as a practical approach in addressing the vulnerabilities of logic locking. Defense-in-depth is a multilayer defense approach where several independent countermeasures are implemented in the device to provide aggregated protection against different attack vectors. Introducing such a multilayer defense model in logic locking is the major contribution of this paper. With regard to this, we first identify the core components of logic locking schemes, which need to be protected. Afterwards, we categorize the vulnerabilities of core components according to potential threats for the locking key in logic locking schemes. Furthermore, we propose several defense layers and countermeasures to protect the device from those vulnerabilities. Finally, we turn our focus to open research questions and conclude with suggestions for future research directions.

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“…In [18], some bits in the chain are dynamically inverted depending on previous output values of selected flip-flops, while [19] inserts random inverters before the shift input on some flops to make extraction of information from cryptographic hardware more difficult. In [20] scan data is also selectively changed, but with XORs. Note that some of these methods don't necessarily prevent access to data; they simply make it more difficult to decode and use.…”

Section: Previous Workmentioning

confidence: 99%

Don't forget to lock your SIB: hiding instruments using P1687

Dworak

Crouch²,

Potter³

et al. 2013

2013 IEEE International Test Conference (ITC)

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IEEE P1687 is a valuable tool for accessing on-chip instruments during test, diagnosis, debug, and board configuration. However, most of these instruments should not be available to an end user in the field. We propose a method for hiding instruments in a P1687 network that utilizes a "locking" segment insertion bit (LSIB) that can only be opened when pre-defined values, corresponding to a key, are present in particular bits in the chain. We also introduce "trap" bits, which can further reduce the effectiveness of brute force attacks by permanently locking an LSIB when an incorrect value is written to the trap's update register. Only a global reset will allow the LSIB to become operable again. In this paper, we investigate the cost and effectiveness of LSIBs and traps in several different configurations and show that these relatively small modifications to the P1687 network can make undocumented instrument access exceedingly difficult.

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Dynamically changeable secure scan architecture against scan-based side channel attack

Cited by 33 publications

References 6 publications

ScanSAT: Unlocking Static and Dynamic Scan Obfuscation

ScanSAT: Unlocking Static and Dynamic Scan Obfuscation

Defense-in-depth: A recipe for logic locking to prevail

Don't forget to lock your SIB: hiding instruments using P1687

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