Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power

Abstract

Signal processing algorithms and architectures can use dynamic reconfiguration to exploit variations in signal statistics with the objectives of improved performance and reduced power consumption. Parameters provide a simple and formal way to characterize incremental changes to a computation and its computing mechanism. This paper examines five parameterized computations which are typically implemented in hardware for a wireless multimedia terminal: 1) motion estimation, 2) discrete cosine transform, 3) Lempel-Ziv lossless compression, 4) 3D graphics light rendering and 5) Viterbi decoding. Each computation is examined for the capability of dynamically adapting the algorithm and architecture parameters to variations in their respective input signals. Dynamically reconfigurable low-power implementations of each computation are currently underway.

Reconfigurable Hardware Architectures for Sequential and Hybrid Decoding

“…3 and 4 that the selection of a constraint length only affects the branch metric ROM address computation in the branch metric unit. By using 8-1 multiplexers in the convolutional encoders in the branch metric unit, the constraint lengths can be reconfigured online from 7,9,11,13,15,17,19, and 21.…”

“…Accepting an overall code rate loss and keeping within a reasonable hardware complexity, CRC-8 and RS (15,11) are employed with a same constraint length 13 convolutional encoder (to enable meaningful performance comparison to the Fano decoder). As illustrated in Fig.…”

“…Every 8-bit column of the aligned block is encoded by the CRC-8 encoder, resulting in an extra 8-bit row. Next, every 4-bit column (each 4-bit data per row in the column are symbols to the RS encoder) of the CRC-8 encoded block is encoded by the RS (15,11) systematic encoder, which will result in 4 more rows of redundant 4-bit data (4 more symbols per column). Finally, 15 convolutional encoders working in parallel will encode the message block row by row, and then the encoded data will be sent through the channel.…”

“…Step 5) Execute two RS (15,11) decoding procedures, one for the 15 symbols that are from the th symbol of 15-row data, the other from the th symbol of 15-row data.…”

“…A time-out counter is used to enable tradeoff of decoding delay versus decoding performance to be made for a particular application by configuring the time-out threshold up to the maximum cycle count of the counter. An FPGA prototype of the decoder is built which is run-time reconfigurable for constraint lengths of 7,9,11,13,15,17,19, and 21, threshold spacings from 0 to 31 and a time-out threshold from 0 to 65535 cycles. Actual hardware decoding performances, in terms of decoding speeds, bit error rates (BERs), and buffer overflow rates, are obtained and comparisons in terms of resource usage and decoding throughput are made with the reconfigurable Viterbi decoder FPGA prototype in [17] and the reduced complexity AVA FPGA implementation in [23].…”