Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes

Hemati, Saied; Banihashemi, Amir H.

doi:10.1109/tcomm.2005.861668

Cited by 61 publications

(31 citation statements)

References 20 publications

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“…To testify the feasibility of the (40, 16) LDPC analog decoder, the simulation model from [13] is improved by taking mismatch of transistors, error brought by IC technics and unit currents (Iu) into account. In the simulation, Soft-XOR gates and Equal gates together implement the BP algorithm over AWGN channel with BPSK modulation.…”

Section: Simulation Results Of the (40 16) Ldpc Analog Decodermentioning

confidence: 99%

An Optimization Method for Designing LDPC Analog Decoders Based on Frequent Subgraph Mining Algorithm

Gao¹,

Lin²,

Dai³

2016

IJSIP

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Section: Simulation Results Of the (40 16) Ldpc Analog Decodermentioning

confidence: 99%

An Optimization Method for Designing LDPC Analog Decoders Based on Frequent Subgraph Mining Algorithm

Gao¹,

Lin²,

Dai³

2016

IJSIP

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“…β controls the sensitivity of the tracker to new information. We will refer to it as the relaxation factor, because this function is the one used in the successive relaxation (SR) algorithm [15]. In the context of iterative decoding, successive relaxation consists in gradually changing the output messages from one iteration to the next (using (5), and interpreting b i as a general input), instead of completely replacing the previous outputs with the new ones.…”

Section: ) Converting Stochastic Streams To Llr Valuesmentioning

confidence: 99%

“…In the context of iterative decoding, successive relaxation consists in gradually changing the output messages from one iteration to the next (using (5), and interpreting b i as a general input), instead of completely replacing the previous outputs with the new ones. It was shown in [15] that SR can improve the performance of iterative decoding algorithms. In the RHS algorithm, the relaxation operation is applied at the input of the variable node.…”

Section: ) Converting Stochastic Streams To Llr Valuesmentioning

confidence: 99%

“…Because it controls the sensitivity of the probability estimate, it sets a bound as to how fast the entire iterative decoder can converge to a codeword. In [15] the authors note that reducing β while increasing the iteration limit has the effect of improving the decoding performance, until it reaches the optimal continuous-time performance. They also note that under a limited number of iterations, there exists an optimal β in terms of performance.…”

Section: ) Converting Stochastic Streams To Llr Valuesmentioning

confidence: 99%

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A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes

Leduc-Primeau

Hemati

Gross

et al. 2009

GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference

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Abstract-This paper presents a Relaxed Half-Stochastic (RHS) low-density parity-check (LDPC) decoding algorithm that uses some elements of the sum-product algorithm (SPA) in its variable nodes, but maintains the low-complexity interleaver and check node structures characteristic of stochastic decoders. The algorithm relies on the principle of successive relaxation to convert binary stochastic streams to a log-likelihood ratio (LLR) representation. Simulations of a (2048, 1723) RS-LDPC code show that the RHS algorithm can outperform 100-iterations floating-point SPA decoding. We describe approaches for lowcomplexity implementation of the RHS algorithm. Furthermore, we show how the stochastic nature of the belief representation can be exploited to lower the error floor.

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“…It has been shown that a relaxed version of BP for analog LDPC codes actually outperforms the digital synchronous version in BSC and AWGN channels [14].…”

mentioning

confidence: 99%

Asynchronous decoding of LDPC codes over BEC

Haghighatshoar

Karbasi

Salavati³

2015

2015 IEEE International Symposium on Information Theory (ISIT)

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Abstract-LDPC codes are typically decoded by running a synchronous message passing algorithm over the corresponding bipartite factor graph (made of variable and check nodes). More specifically, each synchronous round consists of 1) updating all variable nodes based on the information received from the check nodes in the previous round, and then 2) updating all the check nodes based on the information sent from variable nodes in the current round. However, in many applications, ranging from message passing in neural networks to hardware implementation of LDPC codes, assuming that all messages are sent and received at the same time is far from realistic.In this paper, we investigate the effect of asynchronous message passing on the decoding of LDPC codes over a Binary Erasure Channel (BEC). We effectively assume that there is a random delay assigned to each edge of the factor graph that models the random propagation delay of a message along the edge. As a result, the output messages of a check/variable node are also asynchronously updated upon arrival of a new message in its input. We show, for the first time for BEC, that the asymptotic performance of the asynchronous message passing is fully characterized by a fixed point integral equation that takes into account both the temporal and the spatial features of the factor graph. Our theoretical result is reminiscent of the fixed point equation in traditional BP decoding. Also, our simulation results show that asynchronous scheduling reduces decoding time compared to the traditional BP in certain cases in the finite block-length regime.

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Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes

Cited by 61 publications

References 20 publications

An Optimization Method for Designing LDPC Analog Decoders Based on Frequent Subgraph Mining Algorithm

An Optimization Method for Designing LDPC Analog Decoders Based on Frequent Subgraph Mining Algorithm

A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes

Asynchronous decoding of LDPC codes over BEC

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