Dynamics of charge‐pump phase‐locked loops

Abstract

Certain problems in the existing treatment of the stability of charge‐pump phase‐locked loops are identified and addressed in this work. New results concerning the instability, stability, and asymptotic stability of charge‐pump phase‐locked loops are obtained by means of Lyapunov's direct and indirect methods. Closer consideration of the local dynamics provides further insight into the system's patterns of behavior. In particular, the influence of circuit parameters on the nature of the steady‐state orbits is investigated. Copyright © 2012 John Wiley & Sons, Ltd.

Nonlinear Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In Ranges

“…Note that the right-hand side of ( 14) is continuous and piecewise smooth in neighborhood of the origin and discon- 1 The differences between model ( 14) and the models from [17] and [8] can be demonstrated, for example, as follows. The values α = 0.2, β = 1.7, p 0 = −0.18 and u 0 = −0.43 are not taken into account in [17] where the corresponding values a = α, b = β,τ k = p k , and v k = u k are outside of the allowed area in Fig.…”

“…Note that the right-hand side of ( 14) is continuous and piecewise smooth in neighborhood of the origin and discon- 1 The differences between model ( 14) and the models from [17] and [8] can be demonstrated, for example, as follows. The values α = 0.2, β = 1.7, p 0 = −0.18 and u 0 = −0.43 are not taken into account in [17] where the corresponding values a = α, b = β,τ k = p k , and v k = u k are outside of the allowed area in Fig. 2 √ −1 (the editors of IEEE TCOM journal, where two pioneering works [5] and [8] on the CP-PLL had been published, were notified about the above problem and discussed results but did not provide a way to inform journal's readers).…”

“…Extra troubles stem from the fact that straight-forward linearization of available CP-PLL models may lead to incorrect conclusions, because the system is not smooth near the steady state (in fact, it is only piecewise smooth). In [17], stability analysis follows the lines of a Lyapunov approach, however, details of the proof are not presented. Note that nonlinear high-order mathematical models of CP-PLL can also be built by using approximations of exponentials (see, e.g.…”

A self‐calibrated delay‐locked loop with low static phase error

“…However, process variations, operating voltage, temperature, and load factors can cause phase errors in conventional DLLs. Most methods for reducing phase errors focus on current mismatch in charge pump circuit, and several studies have proposed methods to resolve charge and discharge current mismatch problems in the CP circuit . Figure shows the architecture using two push–pull charge pumps (CP1 and CP2) and two replica‐feedback compensators (compensator 1 and compensator 2) .…”

A wideband low‐spur 0.18‐µm CMOS phase‐locked loop with bandwidth calibration

“…The emerging wideband applications have ignited the interest of developing the integrated circuits capable of operation over the range of multi‐gigahertz. The phase‐locked loops (PLLs) are crucial components in many wideband systems and they are widely used as synthesized signal sources and clocks . There exist several challenges for wideband PLL design, and the design trade‐off needs to extend across wide frequency spectrum.…”