E-Band 65nm CMOS Low-Noise Amplifier Design Using Gain-Boost Technique

Katayama, Kosuke; Motoyoshi, Mizuki; Takano, Kyoya; Li, Chen yang; Amakawa, Shuhei; Fujishima, Minoru

doi:10.1587/transele.e97.c.476

Cited by 9 publications

(3 citation statements)

References 18 publications

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“…After giving initial parameter values (for example, by [32]) to the constituent devices, a conjugate gradient engine maximizes an objective function as shown in Fig. 25 [33]. For ultrahigh-speed communication at 10 Gb/s or faster, amplifiers with flat gain and flat group delay over a very wide frequency range are required.…”

Section: Gain and Noise Optimization Of Small-signal Amplifiermentioning

confidence: 99%

Tehrahertz CMOS Design for Low-Power and High-Speed Wireless Communication

Fujishima

Amakawa

Takano

et al. 2015

IEICE Trans. Electron.

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SUMMARY There have recently been more and more reports on CMOS integrated circuits operating at terahertz (≥ 0.1 THz) frequencies. However, design environments and techniques are not as well established as for RF CMOS circuits. This paper reviews recent progress made by the authors in terahertz CMOS design for low-power and high-speed wireless communication, including device characterization and modeling techniques. Low-power high-speed wireless data transfer at 11 Gb/s and 19 pJ/bit and a 7-pJ/bit ultra-low-power transceiver chipset are presented.

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Section: Gain and Noise Optimization Of Small-signal Amplifiermentioning

confidence: 99%

Tehrahertz CMOS Design for Low-Power and High-Speed Wireless Communication

Fujishima

Amakawa

Takano

et al. 2015

IEICE Trans. Electron.

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“…The connection between the MOSFET/RTMOM capacitor and T line is made by the 7th to 9th metal layers. The lengths of the TL stubs and the metal fingers of RTMOM capacitors are determined by a nonmetric optimization process that takes into considering consideration the models of the MOSFET, the RTMOM, the TLs, and the RF pad [2]. Far ends of shunt stubs are terminated by wideband decoupling power lines (0-TLs) of that the lengths are above 140 μm [3].…”

Section: Circuit and Layoutmentioning

confidence: 99%

Compact 138-GHz amplifier with 18-dB peak gain and 27-GHz 3-dB bandwidth

Hara

Watanabe

Sekine

et al. 2015

2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

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VDS VDS VGS VGS Inter-stage matching networks (a) Inter-stage matching networks VDS VGS VGS VDS VDS VGS VGS VDS (b) Fig. 1 Schematic layouts of inter-stage matching networks. (a) Singleended amplifier with "fishbone" layout. (b) Differential amplifier with capacitive cross-coupling with "millipede" layout.Abstract-This paper presents a wi band differential amplifier operating at 138 GHz in 40-nm CMOS. It is composed of five differential common source stages with cross-coupled capacitors. A small-signal gain of 18 dB at 138 GHz and a 3-dB bandwidth of 27 GHz are achieved. It consumes 75 mW from a 0.94-V voltage supply. The die area with balun and pads is 945 × 842 μm 2 and the core size not including input output matching networks is 201 × 284 μm 2 . The small core area is realized by using a refined "fishbone" layout technique.

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“…However, they provide a low range of frequency up to 110 GHz [20]. Katayama et al [21] proposed the 65-nm low noise amplifier of CMOS up to 300 GHz. The authors did not provide detailed parameter extraction methods, however these models are suitable for 2-D planar MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Technique to Simulate the AC/DC Parameters of Trigate FinFETs

Memon,

Rehman,

Bashir

et al. 2024

IEEE Access

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This paper discusses the alternating-current (AC) and direct-current (DC) characteristics of Trigate FinFETs. A modified non linear DC model is proposed to predict I − V characteristics with effect of an efficient technique for the extraction of AC small signal parameters. The extraction of small signal parameters using S-measurements can be developed on advance design system (ADS) software which is based on the electrical behavior of the device. It examines the electrical response as it depends on bias voltages and the extrinsic and intrinsic parameters of Si FinFETs. The approaches discussed here are valid over a range of frequency starting from few Hz up to several tens of GHz. In this paper equivalent circuit procedure has been adopted to compute device AC parameters based on its measured AC response. The characteristics were then simulated by developing a Matlab code based on particle swam optimization (PSO) technique and compared with technology computer aided design (TCAD) data. The results shows that the good agreement are achieved between simulated and TCAD data.

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E-Band 65nm CMOS Low-Noise Amplifier Design Using Gain-Boost Technique

Cited by 9 publications

References 18 publications

Tehrahertz CMOS Design for Low-Power and High-Speed Wireless Communication

Tehrahertz CMOS Design for Low-Power and High-Speed Wireless Communication

Compact 138-GHz amplifier with 18-dB peak gain and 27-GHz 3-dB bandwidth

An Efficient Technique to Simulate the AC/DC Parameters of Trigate FinFETs

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