E-T based statistical modeling and compact statistical circuit simulation methodologies

Chen, J.C.; Hu, Chenming; Wan, C.-P.; Bendix, P.; Kapoor, Ashish

doi:10.1109/iedm.1996.554063

Cited by 39 publications

(11 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is also required to predict performance of the voltage-mode bidirectional link as it was not put on silicon due to unavailability of pad and area. In the model card given by foundry, only few main model parameters (BSIM) are changed to define four process corners (FF,SS,FS,SF) [11]. We also followed the same approach in creating modified model parameters (MMP) corresponding to this process run.…”

Section: Measurement and Simulation Results: Matchingmentioning

confidence: 99%

Low-power current-mode transceiver for on-chip bidirectional buses

Dave

Satkuri

Jain

et al. 2010

Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design

View full text Add to dashboard Cite

This paper presents a current-mode signalling scheme for bidirectional long on-chip interconnects. The transceiver has been fabricated in 180nm CMOS process. Features of the proposed scheme are driver pre-emphasis and lowimpedance termination. While no extra repeater is needed for line lengths up to 8mm long the scheme improves the delay by 34% for 2mm-8mm long lines, compared to bidirectional voltage-mode links. The scheme also improves the power performance for line lengths longer than 2mm, operating at data rates higher than 180Mbps. Measurement results show that delay and power-delay product improve by 18% and 3.7×, respectively, compared to simulation results of the voltage-mode scheme.

show abstract

Section: Measurement and Simulation Results: Matchingmentioning

confidence: 99%

Low-power current-mode transceiver for on-chip bidirectional buses

Dave

Satkuri

Jain

et al. 2010

Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design

View full text Add to dashboard Cite

show abstract

“…BSIM3v3 IV device model parameters from two lots were efficiently generated from Electrical Test data using an equation solver [6]. In addition, device gate, overlap, and junction capacitances were extracted for each die, and kept as a set together with IV parameters.…”

Section: Resultsmentioning

confidence: 99%

“…Therefore, a large number of SPICE device parameters need to be efficiently generated. One possible approach is to extract SPICE parameters directly from Electrical-Test data, using an equation solver technique [6].…”

Section: Methodsmentioning

confidence: 99%

A statistical performance simulation methodology for VLSI circuits

Orshansky

Chen

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

View full text Add to dashboard Cite

A statistical performance simulation (SPS) methodology for VLSI circuits is presented. Traditional methods of worst-case corner analysis lack accuracy and Monte-Carlo simulations cannot be applied to VLSI circuits because of their complexity. SPS methodology is accurate because no statistical information about the device parameter variation is lost. It achieves efficiency by analyzing the smaller circuit blocks and generating the performance distribution for the entire circuit. Circuit evaluation at any specified performance level is possible.

show abstract

“…The device model parameters pertaining to the I-V may be efficiently extracted from electrical-test (E-T) data that is routinely collected in the fab. A large number of device parameter sets may thus be extracted in an efficient way using an equation-solver routine [8]. The model parameters are guaranteed to produce the accurate simulation results for the particular die through a direct substitution of several physically meaningful E-T parameters and optimization of the fitting model parameters to conform to the measured electrical targets ( , Vt for short-channel devices).…”

Section: A Methodologymentioning

confidence: 99%

Direct sampling methodology for statistical analysis of scaled CMOS technologies

Orshansky

Chen

1999

IEEE Trans. Semicond. Manufact.

Self Cite

View full text Add to dashboard Cite

The continued scaling of CMOS technologies introduces new difficulties to statistical circuit analysis and invalidates many of the methodologies developed earlier. The analysis of device parameter distributions reveals multiple sources of parameter correlations, some of which exhibit mutually opposing trends. We found that applying principal component analysis (PCA) to such heterogeneous statistical data may lead to confounding of data and result in underestimation of the total parameter variance. This imposes considerable constraints on the use of several methods of statistical circuit analysis based on PCA. Also, the highly nonlinear relationships between the device parameters become more pronounced and cannot be approximated as linear even in the differential range. As a result, the response surface models based on the linear expansion of the performance variable around the nominal point of the device model parameters may lead to significant prediction errors. To address these difficulties, we propose a conceptually simple and accurate approach of direct sampling that treats the extracted SPICE parameter sets and their physical locations as an inseparable set and thus bypasses the dangerous stage of statistical inferences. We illustrate the methodology by applying it to the statistical analysis of a production CMOS process.

show abstract

E-T based statistical modeling and compact statistical circuit simulation methodologies

Cited by 39 publications

References 4 publications

Low-power current-mode transceiver for on-chip bidirectional buses

Low-power current-mode transceiver for on-chip bidirectional buses

A statistical performance simulation methodology for VLSI circuits

Direct sampling methodology for statistical analysis of scaled CMOS technologies

Contact Info

Product

Resources

About