Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel "Folded Channel Transistor" structure is proposed. The quasi-planar nature of this new variant of the vertical double-gate SO1 MOSFETs [1], [2] simplified the fabrication process. The special features of thie structure ( Fig. 1) are: (1) a transistor is formed in a vertical ultra-thin Si fin and is controlled by a double-gate, which suppresses short channel effects; (2) the two gates are self-aligned and are aligned to the S/D; (3) S/D is raised to reduce the parasitic resistance; (4) new low-temperature gate or ultra-thin gate dielectric materials can be used because they are deposited after the S/D; and (5) the structure is quasi-planar because the Si fins are relatively short. Figure 2 shows the process flow and the SEM pictures at two fabrication steps. Using SO1 wafers as the starting material, Si3N4 and Si02 layer were deposited on the 50-nm SO1 layer. Using 100 keV EB lithography and ashing technique, -20 nm wiide Si fins were patterned and etched. Then, 100-nm P-doped a-Si and 300-nm Si02 were deposited and the result is shown in the top SEM picture. The a-Si becomes polycrystalline later and provides a good contact at the side surface of the Si fin. After delineating the a-Si S/D pattern, SiOz spacers were formed on the sidewalls of the S/D. Through sufficient over-etching, Si02 was removed from the sides of the relatively low Si fins. The top-view SEM picture shows a 15-nm thin Si fin visible in the 50-nm spacer gap, which determines the gate length. After growing 2.5-nm gate oxide on the side surfaces of the Si fin, B-in-situ-doped SiGe (60% Ge) was deposited as the gate. During the gate oxidation, P was diffused from the raised S/D into the Si fin region tlo form S/D extension. We did not use metal electrodes in this experiment so that additional S/D extension diffusion can be optimized. This explains the large parasitic resistance of over 3000 ohmldevice. The W of the devices is twice the height of the Si fins or approximately 100 nm.Typical I-V characteristics of 30-nm gate length are slhown in Fig. 3. In spite of low channel impurity concentration ( 10l6 cm-'), the leakage current caused by DIBL was well suppressed. The Vt roll-off characteristics of a 20-nm Si width devices are shown in Fig. 4. Vt is defined as the gate voltage when Ids= lo-'' A. Good roll-off characteristics are observed for folded channel structure. Figure 5 shows the subthreshold swing dependence on the: Si width. Since the thin body of the double-gate device prevents the punch-through, the folded channel devices show small swings. In Fig. 6, the transconductance (Gm) are plotted with the Si width as a parameter. Interestingly, Gm peaks at 30-nm of Si width. This is because that the thin body increases the parasitic resistance but also can increase the mobility and reduce the charge centrioid, resulting in an optimum in the Si width. Finally, to achieve high current drivability and demonstrate dis...

Effect of Pt bottom electrode texture selection on the tetragonality and physical properties of Ba0.8Sr0.2TiO3 thin films produced by pulsed laser deposition J. Appl. Phys. 112, 044105 (2012); 10.1063/1.4748288 Structural, electrical, and magnetic properties of Mo 1 − x Fe x O 2 ( x = 0 -0.05 ) thin films grown by pulsed laser ablationHighly crystalline thin films of MoS 2 were prepared over large area by pulsed laser deposition down to a single monolayer on Al 2 O 3 (0001), GaN (0001), and SiC-6H (0001) substrates. X-ray diffraction and selected area electron diffraction studies show that the films are quasi-epitaxial with good out-of-plane texture. In addition, the thin films were observed to be highly crystalline with rocking curve full width half maxima of 0.01 , smooth with a RMS roughness of 0.27 nm, and uniform in thickness based on Raman spectroscopy. From transport measurements, the as-grown films were found to be p-type. V C 2015 AIP Publishing LLC. [http://dx.

Well controlled multiple resistive switching states in the Al local doped HfO2 resistive random access memory device Resistive switching mechanisms relating to oxygen vacancies migration in both interfaces in Ti/HfOx/Pt memory devices J. Appl. Phys. 113, 064510 (2013); 10.1063/1.4791695Robust unipolar resistive switching of Co nano-dots embedded ZrO2 thin film memories and their switching mechanismThe influence of Ti top electrode material on the resistive switching properties of ZrO 2 -based memory film using Pt as bottom electrode was investigated in the present study. When Ti is used as top electrode, the resistive switching behavior becomes dependent on bias polarity and no current compliance is needed during switching into high conducting state. This phenomenon is attributed to the fact that a series resistance between Ti and ZrO 2 film, composed of a TiO x layer, a ZrO y layer, and even the contact resistance, imposed a current compliance on the memory device. Besides, our experimental results imply that switching the device into high conducting state is a field driven process while switching back into low conducting state is a current driven process.

Abstract-The authors present a comprehensive characterization method applied to the study of the state-of-the-art 18-m CMOS process. Statistical characterization of gate CD reveals a large spatial intrafield component, strongly dependent on the local layout patterns. The authors describe the statistical analysis of this data and demonstrate the need for such comprehensive characterization. They describe the experimental setup of the novel measurement-based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate circuit modeling and statistical design for increased performance and yield. Characterization is based upon an inexpensive electrically based measurement technique. A rigorous statistical analysis of the impact of intrafield variability on circuit performance is undertaken. They show that intrafield CD variation has a significant detrimental effect on the overall circuit performance that may be as high as 25%. Moreover, they demonstrate that the spatial component of gate CD variability, rather than the proximity-dependent component, is predominantly responsible for speed degradation. In order to reduce the degradation of circuit performance and yield, the authors propose a mask-level spatial gate CD correction algorithm to reduce the intrafield and overall variability and provide an analytical model to evaluate the effectiveness of correction for variance reduction. They believe that potentially significant benefits can be achieved through implementation of this compensation technique in the production environment.

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