Sub 50-nm FinFET: PMOS

Huang, Xuejue; Lee, Wen‐Chin; Kuo, C.; Hisamoto, D.; Chang, Leland; Kedzierski, J.; Anderson, Erik H.; Takeuchi, Hideki; Choi, Yang‐Kyu; Asano, K.; Subramanian, Vivek; King, Tsu‐Jae; Bokor, Jeffrey; Hu, Chenming

doi:10.1109/iedm.1999.823848

Cited by 178 publications

(34 citation statements)

References 5 publications

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“…6,7 Another example is the FinFET, which is also known as the trigate transistor, which utilizes gates to modulate the channel from three sides around the channel to suppress the gate leakage and to prevent short channel effects. 8 There are even transistors which have surrounded gates to modulate the channel from four sides of the channel, such as gate-all-around FETs (Ref. 9) and G 4 -FETs.…”

Section: Improvement Of Drain Breakdown Voltage With a Back-side Gatementioning

confidence: 99%

Improvement of drain breakdown voltage with a back-side gate on AlGaN/GaN high electron mobility transistors

Hwang

Dong

Hsieh

et al. 2015

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Section: Improvement Of Drain Breakdown Voltage With a Back-side Gatementioning

confidence: 99%

Improvement of drain breakdown voltage with a back-side gate on AlGaN/GaN high electron mobility transistors

Hwang

Dong

Hsieh

et al. 2015

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…Poly-Si TFTs utilizing a NW channel with multiple-gate structures have been demonstrated to meet demands in electrical characteristics. [5][6][7][8][9][10][11] However, as the gate length of devices narrows down to the nanometer region, short-channel effects (SCEs) such as off-state leakage, and drain-induced barrier lowering (DIBL) increasingly become unavoidable technical challenges. [12][13][14][15][16][17] Moreover, the control of dopant diffusion in the channel during activation at high temperature becomes more difficult if a lightly doped drain process is not adopted.…”

confidence: 99%

Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Tso¹,

Liu²,

Sheu³

2015

Jpn. J. Appl. Phys.

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Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 µm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; >124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 + 13 mV/V), and a high I ON /I OFF current ratio (>1 ' 10 9 ) under a relatively low voltage condition (V D = 0.3 V, V G = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.

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“…Fragile structured SOI devices are encouraging for escalating CMOS devices into nano-scale regime. One of them is dual-gate FinFET, includes a steep Si fin restrained by self-aligned double gate [2]. The FinFET technology is enticing because the procedure is accessible to implement with existing processing approaches [3].…”

Section: Introductionmentioning

confidence: 99%

Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width

Somra¹,

Mishra²,

Singh³

2015

CAE

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The FinFET transistor structure assures to rejuvenate the chip industry by rescuing it from the short-channel effects that limits the device scalability endured by current planar transistor structures. In this thesis, we report the design, fabrication and physical characteristics of n-channel FinFET with physical gate length of 32nm using visual TCAD (steady state analysis). All the measurements were performed at a supply voltage of 1.5V and 5 nm oxide thickness. We report the drain saturation current is 0.0343453mA at Vg=1V and 0.0410523mA at Vg=1.5V which indicates approximately 20 percent hike in Id with increase in 0.5V gate voltage. We simulate the device for distinct fin thickness from 5 nm to 50 nm. In this thesis we report, for 32 nm gate length FinFET having above 21.33 nm fin width would consequence in short channel effects in spite of having high drain current.

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Sub 50-nm FinFET: PMOS

Cited by 178 publications

References 5 publications

Improvement of drain breakdown voltage with a back-side gate on AlGaN/GaN high electron mobility transistors

Improvement of drain breakdown voltage with a back-side gate on AlGaN/GaN high electron mobility transistors

Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width

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