Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Abstract

Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 µm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; >124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 + 13 mV/V), and a high I ON /I OFF current ratio (>1 ' 10 9 ) under a relatively low voltage condition (V D = 0.3 V, V G = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.

Temperature- and doping-concentration-dependent characteristics of junctionless gate-all-around polycrystalline-silicon thin-film transistors

“…1. 7) First, a 70-nm-thick amorphous silicon (α-Si) layer was deposited by low-pressure Then, sequential conformal deposition was followed by the preparation of 10 nm TEOS and 200 nm in situ n + poly-Si layers by LPCVD, and the poly-Si film was patterned as the gate electrode [Fig. 1(h)].…”

“…[1][2][3][4][5][6] Moreover, the high I on =I off current ratio of ∼10 9 with more stable performance was also demonstrated through a multiple nanowire channel structure. 7) Recently, the junctionless (JL) device has attracted considerable research interest since it has the advantages of a simple fabrication process and the potential to resolve the issues of ultrashort-channel devices in the future, such as the difficult carrier diffusion in the channel and the thermal budget limit. 4,[8][9][10][11][12][13][14][15][16][17] Unlike the traditional inversion mode (IM) transistor, the channel of the JL transistor has the same doping type and concentration as the source and drain (S=D), and the doping concentration is usually up to the magnitude of 10 19 cm −3 .…”

“…In this study, both JL and IM poly-Si NW devices were fabricated by a simplified sidewall spacer process. 2,7) The electrical characteristics at different temperature regions from 77 to 410 K of GAA poly-Si NW JL and IM devices were investigated and compared. In addition, the performances of JL devices with different doping concentrations at different temperatures were also discussed.…”