Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 µm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; >124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 + 13 mV/V), and a high I ON /I OFF current ratio (>1 ' 10 9 ) under a relatively low voltage condition (V D = 0.3 V, V G = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.

The temperature effects of both gate-all-around polycrystalline silicon nanowire (GAA poly-Si NW) junctionless (JL) and inversion mode (IM) transistor devices at various temperatures (77-410 K) were investigated. The electrical characteristics of these devices, such as subthreshold swing (SS), threshold voltage (V th ), and drain-induced barrier lowering (DIBL), were also characterized and compared in this study. Moreover, JL devices with different doping concentrations at various temperatures were also discussed. Both V th and I on showed significant doping concentration dependences for JL devices with doping concentrations of 1 ' 10 19 and 5 ' 10 19 cm %3 . However, the electrical characteristics of JL devices showed less thermal sensitivity when the doping concentration reached 10 20 cm %3 .