Context:Researchers have concentrated their focus on denture wearer's attitude and practice toward denture cleansing despite the fact that they should be more focused on the attitudes of the dentists’ themselves towards patient education at the time of denture delivery. It is an obligation of every dentist to motivate, instruct and provide the means and methods of plaque control for their patients.Aims:The aim was to assess the denture hygiene knowledge, attitudes and practice towards patient education in denture care among dental practitioners (DPs) of Jabalpur city, Madhya Pradesh, India.Material and Methods:A total of 168 dental practitioners completed a comprehensive questionnaire. All participants signed an informed consent before answering the questionnaire. The institutional review committee approved the study.Statistical Analysis:Chi-square test for non-parametric study was employed to determine the statistical difference between the two groups. A P-value of 0.05 was considered to be statistically significant.Results:Most of the subjects were qualified with a bachelor degree 142 (85%). 25 (18%) subjects did not associate oral biofilms on complete denture with conditions like denture stomatitis and other serious systemic diseases. Approximately half of the DPs 69 (48%) and specialists 8 (31%) agreed that explaining denture hygiene instructions to old patients can be very time consuming. A recall program for their patients is of importance according to 39 (27%) of DPs and 3 (12%) specialists.Conclusions:It may be concluded that the study subjects had limited knowledge of denture cleansing materials and denture hygiene importance. Attitudes varied among the subjects when it came to sharing information with their patients.

A double gate FinFET can reduce drain induced barrier lowering and improve threshold (short channel effects). In this paper, a very important geometrical parameter, that is, the fin width of a FinFET has been analyzed. In this article, a double gate n channel FinFET with a gate length of 20nm has been reported. The transfer characteristics of the FinFET at various fin widths have been obtained at a supply voltage of 0.1 V. A comparison is then made between the transfer characteristics of various fin widths. It is observed that, at greater fin widths the drain current also increases as compared to that at shorter fin widths. Thus an increase in device performance is expected, but at the cost of increase in short channel effects. All the simulations have been performed in visual TCAD (Tiber CAD).

In this paper an n-type double gate FinFET at a gate length of 22nm is reported. Here the device performance of FinFET under different gate materials and also under different buried oxides is construed. Firstly, the drain current under different gate materials, with different work functions and SiO 2 being the buried oxide has been obtained. A transfer characteristic curve has then been obtained comparing the drain current for different gate materials at a given supply voltage of 0.5 V. Secondly, the transfer characteristic curve, comparing the drain currents obtained under different buried oxides at 0.5 V supply voltage with Aluminium being the gate has been obtained. And lastly obtained is the device performance for different combinations of gate materials and buried oxides and the results were compared. It can be inferred that, a metal gate and a high k dielectric is what gives a good performance at nanometre ranges. All the simulations have been done in Visual TCAD.

The FinFET transistor structure assures to rejuvenate the chip industry by rescuing it from the short-channel effects that limits the device scalability endured by current planar transistor structures. In this thesis, we report the design, fabrication and physical characteristics of n-channel FinFET with physical gate length of 32nm using visual TCAD (steady state analysis). All the measurements were performed at a supply voltage of 1.5V and 5 nm oxide thickness. We report the drain saturation current is 0.0343453mA at Vg=1V and 0.0410523mA at Vg=1.5V which indicates approximately 20 percent hike in Id with increase in 0.5V gate voltage. We simulate the device for distinct fin thickness from 5 nm to 50 nm. In this thesis we report, for 32 nm gate length FinFET having above 21.33 nm fin width would consequence in short channel effects in spite of having high drain current.

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