EANN: Energy Adaptive Neural Networks

Hassan, S. D.; Attia, Sameh; Salama, Khaled N.; Mostafa, Hassan

doi:10.3390/electronics9050746

Cited by 5 publications

(7 citation statements)

References 16 publications

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“…The remaining bits represent the w − 1 most significant bits of the mantissa m Y to which we append '1' to form the trimmed mantissa m t Y . In (12), the exponent k Y is an unsigned integer and the mantissa m t Y is bounded to the interval [0, 1) assuring that there is no carry from mantisa. Therefore, in the hardware implementation, we can avoid summation in (12) by simply appending bits Y k Y −1 , .…”

Section: The Binary-to-logarithm Conversion Stagementioning

confidence: 99%

“…Approximate computing has emerged as a new paradigm for energy-efficient systems where an acceptable error is induced in computing to achieve more efficient processing [1][2][3][4][5][6]. For example, approximate computing has been used at different system levels [7][8][9][10][11][12][13][14][15][16][17][18] and various approximate arithmetic circuits have been designed to save chip area and energy [8,11,[19][20][21][22][23][24][25][26][27][28].…”

Section: Introductionmentioning

confidence: 99%

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A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing

2021

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Multiplication is an essential image processing operation commonly implemented in hardware DSP cores. To improve DSP cores’ area, speed, or energy efficiency, we can approximate multiplication. We present an approximate multiplier that generates two partial products using hybrid radix-4 and logarithmic encoding of the input operands. It uses the exact radix-4 encoding to generate the partial product from the three most significant bits and the logarithmic approximation with mantissa trimming to approximate the partial product from the remaining least-significant bits. The proposed multiplier fills the gap between highly accurate approximate non-logarithmic multipliers with a complex design and less accurate approximate logarithmic multipliers with a more straightforward design. We evaluated the multiplier’s efficiency in terms of error, energy (power-delay-product) and area utilisation using NanGate 45 nm. The experimental results show that the proposed multiplier exhibits good area utilisation and energy consumption and behaves well in image processing applications.

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Section: The Binary-to-logarithm Conversion Stagementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing

2021

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“…Approximate computing is another promising approach for energy-efficient digital system designs, especially for error-tolerant applications like signal processing in the multimedia domain or neural networks [49]. In this approach, the accuracy requirement of the system is sacrificed at an acceptable level for the sake of performance and energy gains [50].…”

Section: Approximate Stencil Computingmentioning

confidence: 99%

Efficient Acceleration of Stencil Applications through In-Memory Computing

2020

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The traditional computer architectures severely suffer from the bottleneck between the processing elements and memory that is the biggest barrier in front of their scalability. Nevertheless, the amount of data that applications need to process is increasing rapidly, especially after the era of big data and artificial intelligence. This fact forces new constraints in computer architecture design towards more data-centric principles. Therefore, new paradigms such as in-memory and near-memory processors have begun to emerge to counteract the memory bottleneck by bringing memory closer to computation or integrating them. Associative processors are a promising candidate for in-memory computation, which combines the processor and memory in the same location to alleviate the memory bottleneck. One of the applications that need iterative processing of a huge amount of data is stencil codes. Considering this feature, associative processors can provide a paramount advantage for stencil codes. For demonstration, two in-memory associative processor architectures for 2D stencil codes are proposed, implemented by both emerging memristor and traditional SRAM technologies. The proposed architecture achieves a promising efficiency for a variety of stencil applications and thus proves its applicability for scientific stencil computing.

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“…Machine learning techniques vary in their complexity. Multiple optimization techniques have evolved to deal with the machine learning techniques increasing complexity as proposed in [9] and [10]. One of the exploited machine learning techniques in seizure detection is the supervised machine learning algorithm.…”

Section: Introductionmentioning

confidence: 99%

Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration

et al. 2021

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In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). System blocks are implemented to achieve the best trade-off between sensitivity and the consumption of area and power. The proposed seizure detection system achieves 98.38% sensitivity when tested with the implemented linear kernel classifier. The system is implemented on different platforms: such as Field Programmable Gate Array (FPGA) Xilinx Virtex-7 board and Application Specific Integrated Circuit (ASIC) using hardwarecalibrated UMC 65nm CMOS technology. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is lower by at least 65% when compared with the FPGA counterpart. A power-aware system is implemented with FPGAs by the adoption of the Dynamic Partial Reconfiguration (DPR) technique that allows the dynamic operation of the system based on power level available to the system at the expense of degradation of the system accuracy. The proposed system exploits the advantages of DPR technology in FPGAs to switch between two proposed designs providing a decrease of 64% in power consumption.

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EANN: Energy Adaptive Neural Networks

Cited by 5 publications

References 16 publications

A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing

A Hybrid Radix-4 and Approximate Logarithmic Multiplier for Energy Efficient Image Processing

Efficient Acceleration of Stencil Applications through In-Memory Computing

Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration

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