Easily testable image operators: the class of circuits where evolution beats engineers

Sekanina, Lukáš; Růžička, Richard

doi:10.1109/eh.2003.1217658

Cited by 14 publications

(10 citation statements)

References 16 publications

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“…More recently, Garvie and Thompson [2003] have directly evolved simple digital circuits containing a built-in self-test system. Sekanina and Ruzicka [2003] demonstrated that inherently easily testable image filters can be generated automatically for real-world applications. Lohn et al [2003] performed functional recovery of a quadrature decoder after a stuck-at-zero fault for a model of an FPGA.…”

Section: Evolutionary Approaches In the Field Of Testing Of Digital Cmentioning

confidence: 99%

Evolution of synthetic RTL benchmark circuits with predefined testability

Pecenka

Sekanina

Kotásek

2008

ACM Trans. Des. Autom. Electron. Syst.

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This article presents a new real-world application of evolutionary computing in the area of digitalcircuits testing. A method is described which enables to evolve large synthetic RTL benchmark circuits with a predefined structure and testability. Using the proposed method, a new collection of synthetic benchmark circuits was developed. These benchmark circuits will be useful in a validation process of novel algorithms and tools in the area of digital-circuits testing. Evolved benchmark circuits currently represent the most complex benchmark circuits with a known level of testability. Furthermore, these circuits are the largest that have ever been designed by means of evolutionary algorithms. This work also investigates suitable parameters of the evolutionary algorithm for this problem and explores the limits in the complexity of evolved circuits.

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Section: Evolutionary Approaches In the Field Of Testing Of Digital Cmentioning

confidence: 99%

Evolution of synthetic RTL benchmark circuits with predefined testability

Pecenka

Sekanina

Kotásek

2008

ACM Trans. Des. Autom. Electron. Syst.

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“…A number of papers have dealt with the evolutionary image filter design at the hardware level (see e.g. Burian and Takala, 2004;Dumoulin et al, 2000;Erba et al, 2001;Hollingworth et al, 1999;Porter, 2001;Sekanina, 2004;Sekanina and Ruzicka, 2003;Smith et al, 2005;Zhang et al, 2004a,b). In most cases, candidate circuits were evaluated in a reconfigurable device while EA was executed on a personal computer or a cluster of workstations.…”

Section: Introductionmentioning

confidence: 99%

An evolvable hardware system in Xilinx Virtex II Pro FPGA

Vašíček

Sekanina

2007

IJICA

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In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs). Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution by Martinek and Sekanina, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 sec in average.

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“…Garvie and Thompson have directly evolved simple digital circuits from the scratch containing a built-in self-test system [3]. Sekanina and Ruzicka have demonstrated that inherently easily testable image filters can be generated automatically for real-world applications [10]. Lohn et al performed functional recovery of a quadrature decoder after a stuck-at-zero fault for a model of the FPGA [8].…”

Section: Evolutionary Approaches In the Field Of Diagnostics And Testmentioning

confidence: 99%