Evolution of synthetic RTL benchmark circuits with predefined testability

Abstract

This article presents a new real-world application of evolutionary computing in the area of digitalcircuits testing. A method is described which enables to evolve large synthetic RTL benchmark circuits with a predefined structure and testability. Using the proposed method, a new collection of synthetic benchmark circuits was developed. These benchmark circuits will be useful in a validation process of novel algorithms and tools in the area of digital-circuits testing. Evolved benchmark circuits currently represent the most complex benchmark circuits with a known level of testability. Furthermore, these circuits are the largest that have ever been designed by means of evolutionary algorithms. This work also investigates suitable parameters of the evolutionary algorithm for this problem and explores the limits in the complexity of evolved circuits.

Evolvable Hardware

“…For example, because the testability of a candidate circuit can be calculated in a quadratic time, very large benchmark circuits (more than 1 million gates) with predefined testability properties were evolved (Pecenka et al 2008).…”

“…Two examples are briefly described below. A method was described in Pecenka et al (2008), which enables us to evolve large synthetic RTL benchmark circuits with a predefined structure and testability. These benchmark circuits are useful in a validation process of novel algorithms and tools in the area of digital-circuits testing.…”

Wavelet Transform in Fault Diagnosis of Analogue Electronic Circuits

“…Growing complexity of analogue and mixed-level electronic systems (e.g. system-on-chip -SoC) still rises the bar for testing methods (Baker et al, 1996;Balivada et al, 1996;Chruszczyk et al 2006Chruszczyk et al , 2007, 2009, 2011Chruszczyk 2011;Dali & Souders 1989;Kilic & Zwolinski, 1999;Milne et al, 1997;Milor & Sangiovanni-Vincentelli, 1994;Pecenka et al, 2008;Saab et al 2001;Savir & Guo, 2003;Somayajula et al, 1996).…”

Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware

“…of candidate circuits which can be done with a reasonable time overhead. For example, because testability of a candidate circuit can be calculated in the quadratic time complexity, very large benchmark circuits with predefined testability properties (more than 1 million gates) were evolved [36]. • In case that a target system is linear, it is possible to perfectly evaluate a candidate circuit using a single input vector independently of the circuit complexity.…”