Edge Effects in Self-Heating-Related Instabilities in p-Channel Polycrystalline-Silicon Thin-Film Transistors

Abstract

Self-heating-related instabilities have been investigated in p-channel polycrystalline-silicon thin-film transistor, showing an anomalous transconductance (g m ) increase. The g m increase is a fingerprint of edge effects, resulting from a buildup of positive trapped charge in the gate oxide at the channel edges. This was confirmed by the annihilation of such positive charges obtained by sequential hot-carrier bias-stress experiments. From the analysis of the edge effects in devices with different channel lengths, we were able, using 2-D numerical simulations, to determine the size of the defected edge regions to be 400 nm. Index Terms-Hot-carrier (HC) effects, polycrystalline silicon (polysilicon), self-heating (SH), thin-film transistor (TFT).

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

“…On the other hand, since a part of SH degradation occurs at GBs, the less GB N t of unstressed BG ploy-Si TFTs may also contribute to the alleviation of SH degradation. In addition, it is also observed that for normal poly-Si TFTs, as clearly shown in the inset, longer L brings more severe SH degradation at the same p. This is partly attributed to the geometric effect [19], [20], [22] and partly attributed to the higher |E ox | that normal poly-Si TFT with L = 12 μm suffers from.…”

“…The SH degradation depends upon Joule heating generated by high-stress power [15]- [20] and upon E ox generated by stress V g [22]. Therefore, to make the SH degradation comparison between normal poly-Si TFTs and BG poly-Si TFTs more fair, the stress power density p, which equals to stress power divided by the area of the channel, and E ox are employed for the SH discussion.…”