Role of gate oxide thickness in controlling short channel effects in polycrystalline silicon thin film transistors Appl. Phys. Lett. 95, 033507 (2009);

No abstract

Transfer characteristics of polycrystalline silicon (polysilicon) thin film transistors (TFTs) often show a “hump” in subthreshold regime. This effect, also observed in silicon-on-insulator (SOI) transistors, can be attributed to the presence of an enhanced electrical field at edges of the channel, which is related to the specific shape of the edge and its surrounding oxide. In this paper we attempt an analysis of the hump effect in polysilicon TFTs combining electrical measurements and two dimensional numerical simulations, and considering several geometries of the channel edge. The transfer characteristics showing the hump effect are analyzed in terms of a parallel of the main (“bulk”) transistor with two parasitic transistors located at the channel edges. The main and parasitic transistors have different threshold voltages and subthreshold swings and the equivalent parallel circuit reproduces very well the experimental transfer characteristics. The effect on the hump of interface states and oxide fixed charge, localized at the edge regions, is also analyzed and it is found that a degradation of the edge interfaces can easily lead to a hump reduction, thus explaining the large variability in this effect observed for different devices and different processes.

Self-heating-related instabilities have been studied in p-channel polycrystalline-silicon thin-film transistors. The spatial distribution of the interface-state and fixed-oxide-charge densities generated during self-heating experiments has been analyzed and quantitatively determined by using negative-bias temperature stress experiments and 2-D numerical simulations. In addition, the observed asymmetry in the output characteristics with respect to source/drain contact reversal is also perfectly reproduced, confirming the validity of the proposed model.

The threshold voltage (VT) variations induced by the drain bias (Vds) are investigated in polycrystalline silicon thin film transistors (TFTs), with channel length ranging from 20 to 0.4 μm, by combining experimental measurements and two-dimensional (2D) numerical simulations. A careful analysis of the electrical characteristics in both subthreshold and off regime is performed, by taking in account also the effects of the leakage current field enhanced mechanisms on the overall generation-recombination rate. We show that the main causes of VT variations are the drain induced barrier lowering (DIBL) and floating body effects (FBEs), induced by impact ionization. The relative influence of FBEs and DIBL is analyzed by performing numerical simulations with or without including the impact ionization model. A detailed analysis of the 2D Poisson equation has allowed to identify and evaluate the contributions of DIBL and FBEs to the threshold voltage variation when both are present. It is found that, in short channel TFTs at high drain bias, the VT variations can’t be attributed to DIBL effect alone and there is a noticeable contribution of the FBEs to the threshold voltage reduction. From the numerical simulations, the influence of FBEs and DIBL on the electrostatic barrier at source junction and its reduction for increasing Vds is analyzed for long and short channel TFTs.