“Hump” characteristics and edge effects in polysilicon thin film transistors

Abstract

Transfer characteristics of polycrystalline silicon (polysilicon) thin film transistors (TFTs) often show a “hump” in subthreshold regime. This effect, also observed in silicon-on-insulator (SOI) transistors, can be attributed to the presence of an enhanced electrical field at edges of the channel, which is related to the specific shape of the edge and its surrounding oxide. In this paper we attempt an analysis of the hump effect in polysilicon TFTs combining electrical measurements and two dimensional numerical simulations, and considering several geometries of the channel edge. The transfer characteristics showing the hump effect are analyzed in terms of a parallel of the main (“bulk”) transistor with two parasitic transistors located at the channel edges. The main and parasitic transistors have different threshold voltages and subthreshold swings and the equivalent parallel circuit reproduces very well the experimental transfer characteristics. The effect on the hump of interface states and oxide fixed charge, localized at the edge regions, is also analyzed and it is found that a degradation of the edge interfaces can easily lead to a hump reduction, thus explaining the large variability in this effect observed for different devices and different processes.

Optimized single-layer MoS2 field-effect transistors by non-covalent functionalisation

“…Interestingly, as shown in Figure 4(e), the second gm peak appears at the similar VTG (~16 V) in all four samples regardless of VDS, indicating that there is a common reason for the second gm peak with reproducibility. Similar signatures in the transfer characteristics were observed in SOI MOSFETs, 52-56 polysilicon thin film transistors, 57 and gate injection GaN-based transistors. 58 Even in the case of previous studies of SOI MOSFETs, which are more optimized than the MoS2 FETs studied here, the origin of additional transport carriers varied depending on the device structure and materials.…”

P‐22: Fabrication of Oxide‐Based Phototransistors for Visible Light Detection via Nanowire Interfaces

“…Since the band gap of TiO 2 is around 3.2 eV which is similar to that of IGZO and TiO 2 itself shows slight sensitivity to the visible light [8], the defects that remained even after the thermal annealing process increased the photo sensitivity of TiO 2 and IGZO. Also, the existence of a hump in the transfer curve suggests that a parasitic transistor is within the channel layer [9]. This parasitic transistor within the IGZO channel could be deduced to be the TiO 2 nanowire.…”

Parasitic Current Induced by Gate Overlap in Thin-Film Transistors

“…This overlap can generate parasitic currents (“hump”), which, in turn, change the electrical properties [ 14 , 15 , 16 ]. Previous studies have been limited in scope and have investigated individual effects such as the vertical overlap of gate electrodes and S/Ds [ 13 , 17 ] or the parasitic current known as the “hump effect” [ 15 ]. In particular, there have been many reports on the parasitic current that is observed in characteristic anomalies due to defect generation, occurring during reliability tests [ 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 ] or semiconductor fabrication processes [ 26 ].…”