EEPROM device as a reconfigurable analog element for neural networks

Krämer, A.; Hu, Vita Pi‐Ho; Sin, C. K.; Gupta, B. K.; Chu, R.; Ko, P.K.

doi:10.1109/iedm.1989.74274

Cited by 18 publications

(2 citation statements)

References 2 publications

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“…Thereby the memory blocks can be modified accurately independently of each device. It can go back to 1980s that the nonvolatile FG memory is widely used as a synaptic weight storage cell in analog neural networks [5]- [7]. Recently, a prototype mixedsignal, 28×28-binary-input, 10-ouput, 3-layer neuromorphic network based on embedded nonvolatile floating-gate cell arrays redesigned from a commercial 180-nm NOR flash memory have designed, fabricated, and tested for MNIST image classification [8].…”

Section: Introductionmentioning

confidence: 99%

An Enhanced Floating Gate Memory for the Online Training of Analog Neural Networks

Gan

Wang

Chen

et al. 2020

IEEE J. Electron Devices Soc.

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Floating gate (FG) memory has long erasing time, which limits its application as an electronic synapse in online training. This paper proposes a novel enhanced floating gate memory (EFM) by TCAD simulation. Here, three other structures are simulated just for comparison. The simulation results show that the erasing speed is about 34ns while the other three need the time over 1.8ms, which makes the operation speed of long-term potentiation (LTP) more symmetrical to long-term depression (LTD). In addition, both LTP and LTD are approximately linear in the simulation results. The speed, linearity, and symmetry of weight update are the keys to online training of analog neural networks. These excellent performances indicated a potential application of EFM in analog neuro-inspired computing.

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Section: Introductionmentioning

confidence: 99%

An Enhanced Floating Gate Memory for the Online Training of Analog Neural Networks

Gan

Wang

Chen

et al. 2020

IEEE J. Electron Devices Soc.

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show abstract

“…A very similar application pattern exists in the specific area of synaptic memory design for adaptive neural networks. The need for analog storage has been fulfilled with multiple-valued storage in EEPROM structures [10]- [14] or in refreshed capacitors [15]- [22]. For static storage, a bank of binary memory cells coupled with a multiplying digital-to-analog converter (DAC) has been the choice [23]- [25].…”

Section: Introductionmentioning

confidence: 99%

Multiple-valued static CMOS memory cell

Cilingiroglu

Ozelci

2001

IEEE Trans. Circuits Syst. II

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The conventional flip-flop core is generalized to multistability in full static CMOS without compromising the standard binary CMOS features such as ratioless device sizing, negligible static power consumption, and wide noise margins. The proposed multiple-level cell is built with eight devices for three-level operation and necessitates four more devices for each additional level. It can be arranged with a proper address scheme to function as a RAM cell, D-latch, or synaptic memory. Experimental work verifies four-level operation with 3-V supply. Simulations indicate the possibility of six-level storage in 5-V operation. The cell retains noise margins one threshold voltage wide even at such high-level operation. This is made possible by exploiting the dynamic hysteresis associated with the transfer characteristic of an inverter operating with very low rail-to-rail voltage.

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Electronic Circuits for Adaptive Synapses

Mann

Raffel

1992

Neural Networks for Perception

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EEPROM device as a reconfigurable analog element for neural networks

Cited by 18 publications

References 2 publications

An Enhanced Floating Gate Memory for the Online Training of Analog Neural Networks

An Enhanced Floating Gate Memory for the Online Training of Analog Neural Networks

Multiple-valued static CMOS memory cell

Electronic Circuits for Adaptive Synapses

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