Multiple-valued static CMOS memory cell

Cilingiroglu, U.; Ozelci, Y.

doi:10.1109/82.924070

Cited by 21 publications

(9 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This example illustrates why better control over the Si island size is mandatory. A pure CMOS approach is possible but we would have needed at least twelve MOSFETs [ 8 ] when with this confi guration only one MOSFET, one SHT, and two current sources are used. Explanation of quaternary SRAM operation is given in the Supporting Information.…”

Section: Resultsmentioning

confidence: 99%

“…[ 7 ] Specifi cally, one SET/SHT with its multiple threshold voltage points (for each conductance peak) is well suited for MVL, whereas multiple MOSFETs with incremented threshold voltages are required for an equivalent circuit. [ 8 ] Thus, with a higher function density per die area, SET/SHTs would be a perfect fi t into circuit for MVL operation. However, specifi c issues remain to tackle before full SET/ SHTs integration.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Demonstration of Single Hole Transistor and Hybrid Circuits for Multivalued Logic and Memory Applications up to 350 K Using CMOS Silicon Nanowires

Laviéville

Barraud

Arvet

et al. 2016

Adv Elect Materials

View full text Add to dashboard Cite

instance, SET/SHTs used in voltage-based logic system are able to reproduce digital logic based on metal oxide semiconductor fi eld effect transistor (MOSFET) and even extend to multiple-valued logic (MVL) scheme. [ 5 ] Actually, the usual ON and OFF states from a MOSFET can be considered respectively as the resonance peaks and the Coulomb blockade regime of a SET/SHT. As the latter usually displays many peaks, it enables as many ON states such as we speak of MVL. MVL has the advantages over binary logic that using higher radix (e.g., ternary, quaternary, etc.) more information can be handled simultaneously. [ 6 ] Technically, it reduces drastically the number of global interconnects and pinouts in circuits and provides complex operation computed easier than in binary logic. [ 7 ] Specifi cally, one SET/SHT with its multiple threshold voltage points (for each conductance peak) is well suited for MVL, whereas multiple MOSFETs with incremented threshold voltages are required for an equivalent circuit. [ 8 ] Thus, with a higher function density per die area, SET/SHTs would be a perfect fi t into circuit for MVL operation. However, specifi c issues remain to tackle before full SET/ SHTs integration. A major issue to address is these devices have a high output impedance and a low voltage gain which result in a small fan-out and low speed for voltage-based logic circuits. [ 9 ] Fortunately, hybridization of one SET/SHTs in parallel with a MOSFET allows higher gain voltage and high drive current operation while keeping the oscillating output current. [ 10,11 ] Such circuits have been denominated as SETMOS [ 10 ] and pave a way to exploit SET/SHT's inherent characteristics in nanoelectronics, in replacement or in addition to existing complementary metal oxide semiconductor (CMOS) functionalities. [ 12 ] Another issue results from the challenging fabrication of transistors which should have a reproducible Si island of ≈5 nm 3 for proper room temperature (RT) operation. [ 1 ] Originating from the ultimate scaling of MOSFET, 1D nanostructures like nanowires (NWs) now reach channel diameter favorable to quantum confi nement effects at 300 K. [ 13 ] In this way, silicon NW (Si-NW) transistor appears to be a valuable candidate for SET/SHT fabrication and circuit integration. Moreover, the possibility to increase the electrostatic control over the island by a gate surrounding the channel, from

show abstract

Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

Demonstration of Single Hole Transistor and Hybrid Circuits for Multivalued Logic and Memory Applications up to 350 K Using CMOS Silicon Nanowires

Laviéville

Barraud

Arvet

et al. 2016

Adv Elect Materials

View full text Add to dashboard Cite

show abstract

“…MVL circuits are designed in both voltage and current modes. Contrary to their current-mode counterparts, major benefit of designing MVL circuits in the voltage mode is the lower power they consume [1][2][3][4][5][6][7], while current-mode MVL designs provide faster operation compared to their voltage-mode counterparts [8].…”

Section: Introductionmentioning

confidence: 99%

CMOS-compatible structure for voltage-mode multiple-valued logic circuits

Sendi

Sharifkhani

Sodagar

2011

2011 18th IEEE International Conference on Electronics, Circuits, and Systems

View full text Add to dashboard Cite

This paper presents a low-voltage, CMOScompatible, voltage-mode structure for multiple-valued logic circuits. Designed based on a simple and straightforward mechanism and operating in the voltage mode, the proposed structure is suitable for low power applications. Design of both a quaternary inverter and a latch circuit based on the proposed structure are also presented. These circuits are designed in a 0.18-µm CMOS technology with a supply voltage of 1.8V, and dissipate 60nW static power for both circuits. Static noise margin of the inverter is 0.22V.Index Terms-Multiple-valued logic circuit, Quaternary inverter, Quaternary latch, Voltage-mode, MAX circuit.

show abstract

“…K. W. Current implemented quaternary random access memory on traditional CMOS technology with current-mode [3]. Ugur Ç ilingiroglu presented a multiple memory cell building with eight devices for three-valued operation and necessitated four more devices for each additional valued [4]. At the same time, some nontraditional MOSFET device architectures (e.g., Floating gate MOS [5] and SETs MOS [6]) are emerging to implement multiple valued memories.…”

Section: Introductionmentioning

confidence: 99%

Design of a high information-density multiple valued 2-read 1-write register file

Zhang

Wang

Xiong

et al. 2012

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:In this paper, a multiple valued register file (MVRF) with 2-read 1-write circuit is designed in TSMC Low Power 65 nm CMOS. High V TH and Low V TH transistors are organized together to realize a multiple-threshold Literal Gate, and then connect with pass-gates to implement ternary valued register file cell. The information density of the proposed MVRF cell achieves a 61% improvement compared to a standard 6T SRAM, and more than 140% improvement compared to a binary register file. In addition, the quantity of the word line and bit line reduces about 33% compare to a standard 6T SRAM, which also improves the system information density. An 8 × 8 MVRF array have been designed and simulated in terms of power, speed and cell stability. Simulation results show that the MVRF array operates at 1.0 GHz, consuming 1.2 mW at 1.2 V.

show abstract

Multiple-valued static CMOS memory cell

Cited by 21 publications

References 29 publications

Demonstration of Single Hole Transistor and Hybrid Circuits for Multivalued Logic and Memory Applications up to 350 K Using CMOS Silicon Nanowires

Demonstration of Single Hole Transistor and Hybrid Circuits for Multivalued Logic and Memory Applications up to 350 K Using CMOS Silicon Nanowires

CMOS-compatible structure for voltage-mode multiple-valued logic circuits

Design of a high information-density multiple valued 2-read 1-write register file

Contact Info

Product

Resources

About