Effect and model of gate oxide breakdown on CMOS inverters

Impact of single pMOSFET dielectric degradation on NAND circuit performance

“…The gradual channel approximation remains valid for this study as only a small AC signal with a 0V DC bias is applied to the drain when g sdm is measured. Therefore, a similar derivation for the case of a pMOSFET results in (6) where, (7) and, (8) R SD is the total parasitic source and drain resistance measured in series with R ch . It can be assumed R SD is small compared to R ch [25,26] and remains fairly constant after CVS, as the majority of the pMOSFET degradation occurs in the channel [21].…”

“…The effects of dielectric breakdown mechanisms on inverter circuit performance have received recent attention [1][2][3][4][5][6][7][8], yet experimental results (i.e., not simulated) on these effects on other logic gates, such as the NAND gate, are negligible. Furthermore, the focus of reliability studies on the inverter logic circuit has involved the detrimental aspects of a circuit level stress on the DC voltage transfer characteristics (VTC) exclusive of circuit response in the time-domain [1,2,7,8]. In these studies, the type of degradation induced in one or both of the MOSFETs can only be inferred as electrical access to each individual MOSFET was not possible.…”