The influence of temperature on the charge storage and transfer characteristics of the nanocrystalline CdSe embedded Zr-doped HfO 2 high-k dielectric on the p-type Si wafer has been studied. With the increase of temperature, the hole-trapping capacity is increased but the electron-trapping follows the opposite trend, which results in a small reduction of the memory window. From the frequency dispersion measurement result, at high temperatures, holes are loosely trapped at the nanocrystal/high-k interface and electrons are mainly trapped in the bulk nanocrystal. The high temperature induces a larger leakage current because it enhances the charge supply and transfer in the high-k stack. At the low applied voltage, the charge transfer follows the Schottky emission mechanism. In the high, positive gate voltage region, charges are transferred following the Poole-Frenkel mechanism at the low temperature and the Fowler-Nordheim mechanism at the high temperature. The temperature has little effect on the sample's leakage current-gate voltage hysteresis due to the large charge trapping capability. In summary, temperature is an important factor in the operation of the nanocrystals embedded high-k memory device because it affects the charge storage and transfer mechanisms. The quantum dots or nanocrystals embedded gate dielectric stack has been proposed as a possible candidate to replace the polycrystalline Si based floating-gate dielectric structure in nonvolatile memories (NVM's) for the improved reliability.1 This kind of structure retains charges at discrete nanodot sites to avoid the complete loss of trapped charges via a single leakage path in the tunnel oxide layer.
1,2Nanocrystalline Si, ITO, ZnO, MoO x , etc., have been embedded in a SO 2 or high dielectric constant (high-k) dielectric as the charge storage media.2-5 CdSe is a n-type semiconductor with a large work function of 4.8-5.0 eV. 6 The metal-oxide-semiconductor (MOS) capacitor with the nanocrystalline CdSe (nc-CdSe) embedded in SiO 2 has shown the memory function.7 However, SiO 2 is not suitable for future nano sized MOS devices because of the unacceptable large leakage current, which cannot reliably retain trapped charges. 8,9 In order to solve this problem, the SiO 2 layer can be replaced with a physically thicker high-k material, such as HfO 2 or Zr-doped HfO 2 (ZrHfO). [10][11][12] The ZrHfO film has many advantageous dielectric properties over the undoped HfO 2 film, e.g., a higher crystallization temperature, a lower interface state density (D it ), and a larger effective k value.13,14 The nc-CdSe embedded ZrHfO high-k dielectric can store a large number of charges.
15Currently, most studies on the nanocrystals embedded high-k NVMs have been focused on the room temperature performance. Very few publications discuss the temperature effect on this kind of device. 16 However, the temperature of a high-density IC chip during the operation can be much higher than the room temperature.17 Therefore, it is necessary to understand the influence of temperature...