Effect of Design Parameters on Thermomechanical Stress in Silicon of Through-Silicon Via

Abstract

We examined the effect of the design parameters of a through-silicon via (TSV) on the thermomechanical stress distribution at the bottom of the TSV using finite element analysis. Static analyses were carried out at 350 °C to simulate the maximum thermomechanical stress during postplating annealing. The thermomechanical stress is concentrated in the lower region of a TSV, and the maximum stress in silicon occurs at the bottom of the TSV. The TSV diameter and dielectric liner thickness were two important determinants of the maximum stress in the silicon. The maximum stress decreased with decreasing TSV diameter, whereas the effect of aspect ratio was negligible. A thick dielectric liner is advantageous for lowering the maximum stress in silicon. The minimum dielectric thickness resulting in a maximum stress less than the yield stress of silicon was 520, 230, and 110 nm for via diameters of 20, 10, and 5 μm, respectively. The maximum stress also decreased with the thickness of the copper overburden.

Thermal Stress Reduction of Copper Through Silicon Via (TSV) with Annealing

“…3 By simulation using ANSYS software, Wang found that the stress at the via bottom is concentrated at the lower region of the TSV, especially at via bottom corner. 15 In the upper region of the TSV, stress is released by the extrusion of copper when annealing. However, at the bottom part, the stress due to the mismatch in TEC between copper and silicon cannot be released.…”