Effect of Device Variables on Surface Potential and Threshold Voltage in DG-GNRFET

Abstract

<p><em>In this paper we present four simple analytical threshold voltage model for short- channel and length of saturation velocity region (LVSR) effect that takes into account the built – in potential of the source and drain channel junction, the surface potential and the surface electric field effect on double – gate graphene nanoribbon transistors. Four established models for surface potential, lateral electric field, LVSR and threshold voltage are presented. These models are based on the easy analytical solution of the two dimensional potential distribution in the graphene and Poisson equation which can be used to obtain surface potential, lateral electric field, LVSR and threshold voltage. These models give a closed form solution of the surface potential and electrical field distribution as a function of structural parameters and drain bias. Most of analytical outcomes are shown to correlate with outcomes acquired by Matlab simulation and the end model applicability to the published silicon base devices is demonstrated.</em></p>

SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylindrical surrounding gate MOSFET

“…In order to verify the validity of (7), we compared the DIBL values of the previous papers [17,25] with those of this model in Figure 8. Since the static feedback coefficient η is a SPICE parameter having a value of 1 or less, the DIBLs for the minimum value η = 0.1 and the maximum value η = 1.0 are shown in Figure 8 using (7). The solid line denotes the DIBLs at R = 5 nm and t ox = 2 nm and the dotted line at R = 10 nm and t ox = 2 nm.…”

“…FinFETs are structures that increase the controllability of carriers in a channel by fabricating three gates around the channel [4][5][6]. The graphene nanoribbon has been also studied to use in double gate MOSFET [7].…”

Subthreshold swing model using scale length for sub-10 nm junction-based double-gate MOSFETs

“…Although a two-dimensional simulation method is used to analyze the shortchannel effect of sub-10 nm DGMOSFETs, a simple analytical model for circuit analysis has the focus of many studies [8][9][10]. However, most analyses using the analytical model are performed on DGMOSFETs of 20 nm or larger [11][12][13]. In this paper, we present an analytical model of the subthreshold swing (SS) that can be applied at 10 nm or less.…”

Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

“…However, in the transistors of the existing CMOSFET structure, there are difficulties in producing sub-10nm transistors, because of problems such as threshold voltage roll-off, subthreshold swing degradation, and the intensification of drain induced barrier lowering. To solve these problems, not only new devices using GNR (Graphene Nanoribbon) [1], but also multiple gate MOSFETs using silicon have been studied [2,3].…”