Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB).In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICEexhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper

Section: Band-to-band Tunneling Leakage Current Comparisons and Simulmentioning

confidence: 99%

Accurate leakage current models for MOSFET nanoscale devices

Rjoub¹,

Mistarihi²,

Taradeh³

2020

“…Other technological parameters were investigated in our other research paper [26] where we have reported that the base width W b has an important impact on the static current gain β because when we reduce it, the static current gain increases in an important way, while for the emitter length L e when we increase it the static current gain increases slightly. The reduction of transistor size has many advantages in different aspects especially in the technological one, among these advantages we cite the increase of operation speed and improvement of the device reliability by low power consumption, and smaller devices are required for various reasons, for that manufacturers are fabricating them in accelerating way, by example ultrafine transistors are intended for applications such as semiconductor integrated circuits [27,28]. The base layer of the SHBT is the most important and critical layer of this device, because technological parameters related to the base layer such as the width and the doping concentration have an important impact on the static current gain β in comparison to other investigated parameters such as the emitter length and the collector doping concentration.…”

Section: Output Electrical Characteristicsmentioning

confidence: 99%

How does technological parameters impact the static current gain of InP-based Single Heterojunction Bipolar Transistor?

Ouchrif¹,

Baghdad²,

Sahel³

et al. 2019

In telecommunication systems, Heterojunction Bipolar Transistors (HBTs) are used extensively due to their good electrical characteristics. The work presented in this paper aims to enhance the electrical performance of the InP / InGaAs Single Heterojunction Bipolar Transistor (SHBT) in terms of the static current gain β. Silvaco’s TCAD tools were used for the simulation of the output characteristics of the studied electronic device. Initially, we used the interactive tool Deckbuild to define the simulation program and the device editor DevEdit to design the device structure, and we also used the simulator Atlas which allows the prediction of the electrical characteristics of most semiconductor devices. Because of several phenomena occuring within the electronic device SHBT, we added some physical models included in the simulator such as SRH, BBT.STD. Afterwards, we investigated the influence of doping concentrations of the base and the collector Nb and Nc on the electrical performance of the InP/InGaAs SHBT, and particularly in terms of the static current gain β. Finally, based on optimal values of the selected parameters, we have defined an optimized device that has a highest current gain β.

“…The main obstacle of shrinking the dimension of MOSFET is the decrease in gate controllability over the channel due to high electric field [1][2][3][4]. An alternative solution to improve the gate control over the channel is by adding an extra gate [5][6][7][8][9][10]. Multi-gate MOSFETs have been recognized promising candidates for future scaling of MOSFET technologies.…”

Section: Introductionmentioning

confidence: 99%

Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

Kaharudin¹,

Salehuddin²,

Zain³

et al. 2019

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.