Effect of gate length on performance of 5nm node N-channel nano-sheet transistors for analog circuits

Abstract

In this work, the effect of channel length on the performance of an N-channel Nano-sheet Transistor (NST) for analog circuits has been investigated. A fully-calibrated TCAD platform is used to evaluate the performance of NST devices with channel lengths ranging from 10 nm to 240 nm. The maximum transconductance measured is 0.65 mS for gate length of 24 nm. In addition, the transconductance efficiency ranging from 3 V −1 to 38 V −1 is observed. Intrinsic gain increases from 7.3 to 121.65 as the gate length is varied from 10 nm to 240 nm. For 12 nm gate length, a unit gain frequency of 565 GHz is observed. NST with 24 nm exhibits Gain Frequency Product value of 5.3 THz. The gain-to-power efficiency improvement from 0.048 µA −1 to 2.16 µA −1 is observed. A reversal of relationships of transconductance and other performance parameters with gate length is observed at 24 nm gate length.

Air-spacers as analog-performance booster for 5 nm-node N-channel nanosheet transistor

“…Gain-frequency product (GFP), defined as, GFP = A v × f T ; is also a parameter that shows the gain as well as the speed capabilities of a transistor [45]. Larger the value of GFP is, the superior is the transistor's performance.…”

“…Transconductance-frequency product (TFP) and the gain-transconductance-frequency product (GTFP) parameters are defined as: TFP = (g m /I D ) × f T ; and GTFP = A v × (g m /I D ) × f T , respectively [45]. Larger the values of TFP and GTFP, the better is a NST device for analog applications.…”

“…The quasi-ballistic effects on the charge carrier mobility are included by the use of low-field ballistic mobility model [40,44]. The stress-induced mobility enhancements are included by the use of piezo model in TCAD [40,45]. The degradation of mobility due to the trap-charges is incorporated by activating the calculations of transverse electric field (E normal ) along with the remote-phonon-scattering, thin-layer, and inversion & accumulation-layer mobility models [45].…”

“…The stress-induced mobility enhancements are included by the use of piezo model in TCAD [40,45]. The degradation of mobility due to the trap-charges is incorporated by activating the calculations of transverse electric field (E normal ) along with the remote-phonon-scattering, thin-layer, and inversion & accumulation-layer mobility models [45]. The calibration of TCAD model involves adjustment of the parameters used for different material and models [39,45] The transfer characteristics (I DS vs. V GS ), obtained for both of the N-channel and P-channel NST devices using the calibrated TCAD model, are shown in figure 3.…”

The gate length effect of high-performance monolayer SiAs2 FETs

“…As L gate = 50 nm, r o reaches the maximum of 2 × 10 5 Ω for p-FET and 10 5 Ω for n-FET. Long-gate monolayer SiAs 2 FETs exhibit high output resistance, which would be better suited in analog circuits, such as current mirrors [24].…”