Effect of Ge Mole Fraction on Electrical Parameters of Si1−xGex Source Step-FinFET and its Application as an Inverter

Saha, Rajesh; Bhowmick, Brinda; Baishya, Srimanta

doi:10.1007/s12633-018-9846-8

Cited by 11 publications

(2 citation statements)

References 33 publications

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“…The different configurations of Si 1-x Ge x utilized by researchers so far provide a balance between electron mobility and hole mobility of Ge are summarized in Table 2. Thermoelectric Applications Schottky Barrier [17] Leakage Current Improving Applications SiGe Shell [18] Ultrathin P-FinFET Applications Sub 100 nm Tunnel FET [19] DRAM Applications Heterojunction Tunnel Model [20] Optimize Tunnel Logic Inverter Applications Negative Capacitance [21] Tradeoffs in Energy Delay Low Power Switching Applications Heterogeneous Tunnel Dielectric [22] Device Reliability Applications Gate Surrounding Channel [23] 6-Transistor SRAM Cell Applications Vertical Slit [24] 3-DM Integration Applications Fully Depleted SOI [25] Radio Frequency Applications SiGe [26] Enhancing Speed and High-Volume Optical Interconnect Applications Si 0.6 Ge 0.4 [27] Step-FinFET and Inverter Applications Gate All-Around [28] SCE Improvement Applications Double-Gate [29] High Pass Filter Applications Double-Gate [30] Core Insulator Applications Double-Gate [31] Fully Depleted SOI Applications Dual-Gate [32] Source Follower Applications Memristor [33] Reducing Power Consumption and Increasing IC Performance Applications.…”

Section: Literature Reviewmentioning

confidence: 99%

Analysis of Different Configurations of Si1-xGex for Double-Gate MOSFETs and Its Future Applications

Singh

Kumar

2023

Advances in Transdisciplinary Engineering

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The major drawbacks of basic electronic components i.e., Vacuum Tubes used before the 1960s were a large size and the inability of these to be scaled down further. With the emphasis shifting to scaling down we came across the MOSFETs in single-gate configuration since the 1960s, they are utilized nowadays in the nanometer region for keeping the high-performance level but still, these single-gate configurations of MOSFETs suffer from different parameters such as coupling, interfacing, channel mobility, channel orientation, switching delay, latch-up and leakage current, short channel effects (DIBL, GIDL, subthreshold swing) and volume inversion and this has led to decrease in inversion charge, increase in leakage current and reduction in the drive current leads us to the exploration of the double-gate configuration of MOSFET and on further exploration it leads us to the novel and higher mobility channel materials such as Si1-xGex which can perform and even shows better results than prevailing single-gate MOSFETs. This paper analyses the different configurations of Si1-xGex for double-gate configuration of MOSFETs and its Future Applications.

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Section: Literature Reviewmentioning

confidence: 99%

Analysis of Different Configurations of Si1-xGex for Double-Gate MOSFETs and Its Future Applications

Singh

Kumar

2023

Advances in Transdisciplinary Engineering

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“…This device D 0 and subsequently all other devices implement a tri-layered channel structure consisting of two strained silicon layers of 1.5 nm each embedding a 3 nm layer of Si 1-x Ge x in between. The SiGe layer has a mole fraction of x = 0.4 as per Khiangte et al [14] and Saha et al [22]. The HOI channel region is then extended for 1 nm on either side without the gate oxide and the conductor layer on top to introduce a gate underlap structure of 1 nm, termed as D 1 .…”

Section: Device Structure and Theorymentioning

confidence: 99%

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Datta,

Nanda,

Sankar Dhar

2023

Phys. Scr.

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With sub-22 nm technology nodes, the short channel effects (SCEs) arose in FinFETs, which hindered the further scaling of devices. The leakage currents became detrimental with scaling of the gate oxide thickness below 2 nm, hence the demand for control of leakage currents due to corner effects in the sidewalls of FinFETs. Research suggested use of gate underlap (GUL) architectures to suppress the leakage currents. The objective of this paper is to utilize a GUL structure in a 10 nm gate length Heterostructure-On-Insulator (HOI) FinFET, encompassing a three layered strained channel architecture to enrich the drive currents. Different structures with GUL lengths of 1 nm, 3 nm and 5 nm are designed to study the electrical characteristics besides the effects of leakage currents and other SCEs. A noteworthy decrease is observed in the leakage currents with increasing GUL lengths. However, it also leads to decrease of drive currents of the devices. A trade-off between the enhanced dimensions of source/drain along with an optimized GUL length proves beneficial in the strained silicon channel devices. The 10 nm HOI device employing a 3 nm GUL with height/width of source/drain at 8 nm provides drive currents and leakage currents at par with the 10 nm HOI device with no underlap. But with higher Ion/Ioff current ratio and lower SCEs, this device with 3 nm underlap decreases corner effects and is observed from the electron velocity and total current density contours leading to faster switching speeds and optimized device performance towards semiconductor industry.

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RF analysis and temperature characterization of pocket doped L-shaped gate tunnel FET

2019

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Effect of Ge Mole Fraction on Electrical Parameters of Si1−xGex Source Step-FinFET and its Application as an Inverter

Cited by 11 publications

References 33 publications

Analysis of Different Configurations of Si1-xGex for Double-Gate MOSFETs and Its Future Applications

Analysis of Different Configurations of Si1-xGex for Double-Gate MOSFETs and Its Future Applications

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

RF analysis and temperature characterization of pocket doped L-shaped gate tunnel FET

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