Effect of High-K Spacer on the Performance of Non-Uniformly doped DG-MOSFET

Swain, Sanjit Kumar; Das, Satish Kumar; Biswal, Sudhansu Mohan; Adak, Sarosij; Nanda, Umakanta; Sahoo, Asmit Amlan; Navak, Debasish; Baral, Biswajit; Tripathy, Debi Prasad

doi:10.1109/devic.2019.8783740

Cited by 11 publications

(3 citation statements)

References 21 publications

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“…Beyond the excess of off‐state current, the applied gate voltage causes charges to build up close to the surface. [ 16–23 ]…”

Section: Introductionmentioning

confidence: 99%

“…Beyond the excess of off-state current, the applied gate voltage causes charges to build up close to the surface. [16][17][18][19][20][21][22][23] The body region of the device should remain fully depleted in the junctionless transistor for proper off-state of the device. To achieve this condition, the work function difference between the gate material and substrate must be high enough so that the resulting electric field can maintain the device in a fully depleted condition.…”

Section: Introductionmentioning

confidence: 99%

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Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

Abrishami

Orouji

2023

Physica Status Solidi (a)

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This work presents a double‐gate junctionless metal‐oxide field‐effect transistor (JLT) in a 20 nm regime by modifying central potential. In the proposed device, the off‐state current is reduced due to modifying the potential in the middle of the channel. The proposed structure is called as a modified central potential junctionless transistor (MCP‐JLT). The suggested device embeds two dielectric pockets (DPs) into the middle of the channel. The proposed technique has several effects on the proposed structure. Also, the impact of the DPs into the channel on the performance device is discussed. The proposed MCP‐JLT structure decreases the off‐state current (IOFF) by three orders of magnitude; besides, it can suppress the lateral electric field and also slightly reduces the drive current (ION), and reduces subthreshold swing (SS) compared to a typical junctionless FET (C‐JLT). Furthermore, the effect of the gate insulator materials on the proposed device's performance is discussed.

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“…Beyond the excess of off‐state current, the applied gate voltage causes charges to build up close to the surface. [ 16–23 ]…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

Abrishami

Orouji

2023

Physica Status Solidi (a)

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“…To overcome those device fabrication problems, different approaches like multi-gate device architecture [20] and a dielectric modulating technique (replacing thinner silicon oxide (SiO 2 ) gate insulator with high-k dielectric constant material) [21] have been proposed. High-k gate oxide makes thicker equivalent oxide thickness (EOT), and it is used to over com quantum mechanical tunneling and SCEs under the nanoscale regime of gate oxide thickness [13] [22] [23]; this can be obtained using eq. (1) [13].…”

mentioning

confidence: 99%

Impact of interface trap charges on Junctionless double and triple metal gate High-k Gate All Around Nanowire FET based Alzheimer Biosensor

Chaujar

Yirak

2021

Preprint

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In this work, junctionless double and triple metal gate high-k gate all around nanowire field-effect transistor-based APTES biosensor has been developed to study the impact of ITCs on device sensitivity. The analytical results were authenticated using ‘‘ATLAS-3D’’ device simulation tool. Effect of different interface trap charge on the output characteristics of double and triple metal gate high-k gate all around junctionless NWFET biosensor was studied. Output characteristics, like transconductance, output conductance,drain current, threshold voltage, subthreshold voltage and switching ratio, including APTES biomolecule, have been studied in both devices. 184% improvement has been investigated in shifting threshold voltage in a triple metal gate compared to a double metal gate when APTES biomolecule immobilizes on the nanogap cavity region under negative ITCs. Based on this finding, drain off-current ratio and shifting threshold voltage were considered as sensing metrics when APTES biomolecule immobilizes in the nanogap cavity under negative ITCs which is significant for Alzheimer's disease detection. We signifies a negative ITC has a positive impact on our proposed biosensor device compared to positive and neutral ITCs.

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Interface Trap Charge Analysis of Junctionless Triple Metal Gate High-k Gate All Around Nanowire FET-Based Biotin Biosensor for Detection of Cardiovascular Diseases

Yirak

Chaujar

2021

Lecture Notes in Electrical Engineering

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Effect of High-K Spacer on the Performance of Non-Uniformly doped DG-MOSFET

Cited by 11 publications

References 21 publications

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

Impact of interface trap charges on Junctionless double and triple metal gate High-k Gate All Around Nanowire FET based Alzheimer Biosensor

Interface Trap Charge Analysis of Junctionless Triple Metal Gate High-k Gate All Around Nanowire FET-Based Biotin Biosensor for Detection of Cardiovascular Diseases

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