Effect of High-Pressure Inert Gas Annealing on AlON/Ge Gate Stacks

Tabata, Toshiyuki; Nagashio, Kosuke; Toriumi, Akira

doi:10.1143/apex.5.091002

Cited by 3 publications

(2 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…3.3. 77,78) So GeO desorption could be reduced and the interface properties might be improved by fine-tuning the N profile in GeO 2 . As we did not have an appropriate technique for the optimum nitridation of Ge for N not to be located at the interface, we stopped studying the GeON gate stack.…”

Section: Materials Approachmentioning

confidence: 99%

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

Toriumi

Nishimura

2017

Jpn. J. Appl. Phys.

Self Cite

147

112

View full text Add to dashboard Cite

CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is expected. This size scaling will end sooner or later, however, because the typical size is approaching the atomic distance level in crystalline Si. In addition, it is said that electron transport in FETs is ballistic or nearly ballistic, which means that the injection velocity at the virtual source is a physical parameter relevant for estimating the driving current. Channel-materials with higher carrier mobility than Si are nonetheless needed, and the carrier mobility in the channels is a parameter important with regard to increasing the injection velocity. Although the density of states in the channel has not been discussed often, it too is relevant for estimating the channel current. Both the mobility and the density of states are in principle related to the effective mass of the carrier. From this device physics viewpoint, we expect germanium (Ge) CMOS to be promising for scaling beyond the Si CMOS limit because the bulk mobility values of electrons and holes in Ge are much higher than those of electrons and holes in Si, and the electron effective mass in Ge is not much less than that in III-V compounds. There is a debate that Ge should be used for p-MOSFETs and III-V compounds for n-MOSFETs, but considering that the variability or nonuniformity of the FET performance in today's CMOS LSIs is a big challenge, it seems that much more attention should be paid to the simplicity of the material design and of the processing steps. Nevertheless, Ge faces a number of challenges even in case that only the FET level is concerned. One of the big problems with Ge CMOS technology has been its poor performance in n-MOSFETs. While the hole mobility in p-FETs has been improved, the electron mobility in the inversion layer of Ge FETs remains a serious concern. If this is due to the inherent properties of Ge, only p-MOSFETs might be used for device applications. To make Ge CMOS devices practically viable, we need to understand why electron mobility is severely degraded in the inversion layer in Ge n-channel MOSFETs and to find out how it can be increased. In the Si CMOS technology, the SiO 2 /Si interface has long been investigated and cannot be ignored even after the introduction of high-k gate stack technology. In that sense, the GeO 2 /Ge interface should be intensively studied to make the best of Ge's advantages. Therefore we first discuss the GeO 2 /Ge interface with regard to its physical and electrical characteristics. When we regard Ge as a channel material beyond Si for high performance ULSIs, we also have to seriously consider the gate stack scalability and reliability. The source/ drain engineering, as well as the gate stack formation, is another challenge in Ge MOSFET design. Both the higher metal/Ge contact resistance and the larger p/n junction leakage current may be the consequences of Ge's intrinsic properties because they are derived from the strong Fermilevel pinning and the narrow energy band gap, respectively. Even if the...

show abstract

Section: Materials Approachmentioning

confidence: 99%

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

Toriumi

Nishimura

2017

Jpn. J. Appl. Phys.

Self Cite

147

112

View full text Add to dashboard Cite

show abstract

“…Notably, C Lee et al has revealed a novel high-pressure oxidation (HPO) of Ge would dramatically improve Ge/GeO 2 interface [7]. Besides of that, post deposition annealing (PDA) by varying different annealing parameters such as annealing ambient, temperature and duration is widely used for various Ge/dielectric interface reparement such as HfTiON/Ge [11], Al 2 O 3 /Ge [12,13], HfO 2 /Ge [14], Y 2 O 3 /Ge [15], and AlON/ Ge [16]. For example, X Zou et al have reported that wet-N 2 annealing can greatly suppress the growth of unstable low-k GeO x at the high-k HfTiON/Ge interface, thus resulting in less interface states and di electric charges [11].…”

Section: Introductionmentioning

confidence: 99%

Band bending analysis of charge characteristics at GeO₂/Ge interface by x-ray photoemission spectroscopy

Zhang

Lou

Xie

et al. 2018

J. Phys. D: Appl. Phys.

View full text Add to dashboard Cite

Ge complementary metal oxide semiconductor (CMOS) is promising for scaling beyond the Si CMOS due to its higher carrier mobility than Si. Analogue to classical SiO 2 /Si system in the Si CMOS technology, various interface/bulk charges including interface traps (Q it ), fixed surface state charges (Q f ), trapped positive charges (Q pt ) and negative charges ((Q nt ) in GeO 2 /Ge system are also crucial both for the device performance and reliability. Because small amounts of charges would cause photoemission peak shift characterized by x-ray photoemission spectroscopy (XPS), it offers a feasible way to evaluate various charge densities by measuring the band bending in Ge substrate from Ge 3d core-level energy shift at GeO 2 /Ge interface. Moreover, photoemission peak shifts as a function of x-ray irradiation time have been widely accepted for characterization of charge trapping phenomena. Here, we report a band bending analysis at GeO 2 /Ge interface of featuring vital charge characteristics for diverse device applications by XPS. HF-last cleaned Ge surface was verified to tend to be p-type, irrespective of the bulk conductivity. The n-Ge/GeO 2 interfaces exhibit a reduction of upward band bending evolution of Ge substrate, while p-type-Ge/GeO 2 interfaces indicate a reduction of downward band bending evolution when comparing the different quality GeO 2 / Ge interfaces. Based on the requirement of surface charge neutrality, such observation has been attributed to a dominated passivation effect to negatively charged interface traps and the positive fixed surface state charges, respectively. Moreover, a time evolution of Ge 3d and O 1s signals reveals a progressive band bending modification at GeO 2 /Ge interface, clarifying the thermally-grown GeO 2 also contains electron traps (Q nt ). Ultimately, the four types of charges relying on the GeO 2 /Ge quality were modeled to correlate with the observed Ge band bending evolution, which would impact both the device operation and reliability.

show abstract

Effect of dimethylaluminumhydride-derived aluminum oxynitride passivation layer on the interface chemistry and band alignment of HfTiO-InGaAs gate stacks

Deng

Chen

et al. 2013

Apl Materials

View full text Add to dashboard Cite

In this letter, the reduction and removal of surface native oxide from as-received InGaAs surface by using dimethylaluminumhydride-derived aluminum oxynitride (AlON) passivation layer prior to HfTiO deposition is proposed to solve Fermi level pinning issue. It has been revealed that complete consumption of native oxides of AsOx and GaOx at the InGaAs surface, but no effect to InOx, has been realized after metalorganic chemical vapor deposition AlON at 300 °C. X-ray photoelectron spectroscopy observations of HfTiO/InGaAs gate stacks demonstrate that introducing AlON layer can suppress the regrowth of native oxide at the interface. In addition, the dependence of the valence band spectra of HfTiO/InGaAs gate stacks on AlON passivation layer has been discussed in detail.

show abstract

Effect of High-Pressure Inert Gas Annealing on AlON/Ge Gate Stacks

Cited by 3 publications

References 24 publications

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

Band bending analysis of charge characteristics at GeO₂/Ge interface by x-ray photoemission spectroscopy

Effect of dimethylaluminumhydride-derived aluminum oxynitride passivation layer on the interface chemistry and band alignment of HfTiO-InGaAs gate stacks

Contact Info

Product

Resources

About

Effect of High-Pressure Inert Gas Annealing on AlON/Ge Gate Stacks

Cited by 3 publications

References 24 publications

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

Band bending analysis of charge characteristics at GeO2/Ge interface by x-ray photoemission spectroscopy

Effect of dimethylaluminumhydride-derived aluminum oxynitride passivation layer on the interface chemistry and band alignment of HfTiO-InGaAs gate stacks

Contact Info

Product

Resources

About

Band bending analysis of charge characteristics at GeO₂/Ge interface by x-ray photoemission spectroscopy