Effect of interface states on sub-threshold response of III–V MOSFETs, MOS HEMTs and tunnel FETs

Kao, Wei-Chieh; Ali, A.; Hwang, Eunju; Mookerjea, S.; Datta, Suman

doi:10.1016/j.sse.2010.07.018

Cited by 33 publications

(13 citation statements)

References 5 publications

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“…9 Although numerous publications have reported on epitaxially grown III−V nanowires including characterization of the electrical and structural properties, 9−16 detailed studies of the nanowire transistor MOS gate stack, including the determination and optimization of the interface trap density (D it ), are still seldom reported. 17, 18 Indeed, a low D it is of utmost importance for high-performance MOSFETs since charge trapping at interface states restricts the Fermi level movement, which significantly degrades the transistor subthreshold slope 19 and extrinsic transconductance. 20 It is well-known that the nanowire characteristics strongly depend on the nanowire growth conditions.…”

mentioning

confidence: 99%

Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

Babadi²,

Jacobsson

et al. 2016

Nano Lett.

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In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the Dit profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed.

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mentioning

confidence: 99%

Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

Babadi²,

Jacobsson

et al. 2016

Nano Lett.

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“…These interface states can impede charge transport through the interface and reduce the carrier lifetime, hence detrimentally affecting device functionality . The passivation of interface states has always been an important consideration for realizing high performance heterojunctions . Despite the importance of interface states in device functionality, to the best of our knowledge, the density and distribution of interface states in the electronic structure of the GaP/Si(001) heterojunction has not been thoroughly investigated.…”

Section: Introductionmentioning

confidence: 99%

“…15,[24][25][26][27] The passivation of interface states has always been an important consideration for realizing high performance heterojunctions. [28][29][30][31][32][33][34][35] Despite the importance of interface states in device functionality, to the best of our knowledge, the density and distribution of interface states in the electronic structure of the GaP/Si(001) heterojunction has not been thoroughly investigated.…”

Section: Introductionmentioning

confidence: 99%

Electronic structure of GaP/Si(001) heterojunctions and the role of hydrogen passivation

Meidanshahi¹,

Zhang²,

Zou³

et al. 2019

Progress in Photovoltaics

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Epitaxially grown single crystal GaP on Si is of considerable interest due to being nearly lattice matched to Si, making it attractive for III‐V/Si solar cells. GaP has been used as a buffer layer for III‐V/Si solar cells and also in selective contact Si solar cells. The performance and functionality of such devices are strongly influenced by the presence of localized states at the GaP/Si interface. Here, we examine the electronic structure of GaP/Si(001) heterojunctions and the effect of hydrogen (H) passivation at the interface, in contrast to interface mixing, through density functional theory calculations. Our calculations show that due to the heterovalent mismatch nature of the GaP/Si interface, there is a high density of localized states at the abrupt GaP/Si interface due to the excess charge associated with heterovalent bonding, as reported elsewhere. We find that the addition of H leads to additional bonding at the interface, which mitigates the charge imbalance, and greatly reduces the density of localized states, leading to a nearly ideal heterojunction. A similar result is found with a completely intermixed interface (alternating cation and anion bonding) in terms of low interface state density. However, when the intermixing occurs through single‐layer or double‐layer terraces, the benefits of intermixing are lost and the interface state density reverts more to the abrupt interface case.

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“…Since the growth of nitride material is difficult, recently some HEMTs are reported to be fabricated using InAs and/or GaAs material [9]. Among these, Buried Channel InAs MOSFET is notable due to the fact that it has oxide gate which will reduce the gate leakage current [10]. Self-consistent analysis is yet to be done for this device to investigate the effect of material composition and gate dielectric variation on device performance.…”

Section: Introductionmentioning

confidence: 99%

Self-consistent C-V characterization of depletion mode buried channel InGaAs/InAs Quantum Well FET incorporating strain effects

Ahmed

Niaz

Alam

et al. 2012

2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)

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We investigatedCapacitance-Voltage (C-V) characteristics of the Depletion Mode Buried Channel InGaAs/InAs Quantum Well FET by using Self-Consistent method incorporating Quantum Mechanical (QM) effects. Though the experimental results of C-V for enhancement type device is available in recent literature, a complete characterization of electrostatic property of depletion type Buried Channel Quantum Well FET (QWFET) structure is yet to be done. C-V characteristics of the device is studied with the variation of three important process parameters: Indium (In) composition, gate dielectric and oxide thickness. We observed that inversion capacitance and ballistic current tend to increase with the increase in Indium (In) content in InGaAs barrier layer.

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Effect of interface states on sub-threshold response of III–V MOSFETs, MOS HEMTs and tunnel FETs

Cited by 33 publications

References 5 publications

Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

Electronic structure of GaP/Si(001) heterojunctions and the role of hydrogen passivation

Self-consistent C-V characterization of depletion mode buried channel InGaAs/InAs Quantum Well FET incorporating strain effects

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