Effect of interface states on the dc characteristics of short channel metal-semiconductor field effect transistor

Effect of deep-level impurities on the drain characteristics of short-channel metal-semiconductor field effect transistors

“…The effect of the presence of trapping states on the electrical characteristics of metal-semiconductor field effect transistors has been the subject of considerable interest in the recent past [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. So far two types of state have been considered for the purpose of device modelling, namely, the deep-impurity states in the semiconductor [1][2][3][4] and interface states at the gate contact of the device [12][13][14]. The enhanced temperature sensitivity of the threshold voltage has been attributed to deep levels [1].…”

“…The models discussed in [3] and [4] include only the deep levels, though one cannot disregard the presence of interface states at the gate contact. The extent to which these devices are influenced by interface states has been discussed in a number of investigations [12][13][14]. One can therefore look for a further generalization by taking into account the presence of both the interface states and deep levels and study in depth the drain characteristics of the device.…”