The temperature dependence of threshold voltage of metal‐semiconductor field effect transistors is studied considering a generalised interface state model and an uneven distribution of interface and bulk impurity states. The analysis predicts a sharp variation of threshold voltage with temperature which is in contrast to the conventionally known temperature dependence due to the band gap energy. The theoretical results are found in agreement with previous experimental findings.

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The role of deep-level impurities in the drain characteristics of a short-channel metal-semiconductor field effect transistor has been investigated. The drain current of the device has been evaluated for different values of deep-level density and at different temperatures ranging from 300 to 400 K. The presence of deep levels gives rise to an excess drain current resulting from the electronic excitations from the defect levels. The increase in the temperature enhances the current due to increasing ionization of the defects. An analytical expression for the channel conductance is also derived and it is found to be a function of deep-level concentration besides other nonidealities such as interface states and interfacial oxide layer. The effect of gate length shortening also reveals significant changes in the current and conductance.