Temperature Dependence of Threshold Voltage of Metal-Semiconductor Field Effect Transistors in the Presence of an Uneven Distribution of Interface and Bulk States

Abstract

The temperature dependence of threshold voltage of metal‐semiconductor field effect transistors is studied considering a generalised interface state model and an uneven distribution of interface and bulk impurity states. The analysis predicts a sharp variation of threshold voltage with temperature which is in contrast to the conventionally known temperature dependence due to the band gap energy. The theoretical results are found in agreement with previous experimental findings.

Ageing of metal-semiconductor field effect transistors

“…is the interface trapped charge density [2], D it is the interface state density and φ 0 is the neutral level [6]; Q f is the fixed charge density; and Q si is the trapped charge density at the liberated silicon atoms and other terms have their usual meanings. In the case of silicon MESFETs having a thin SiO 2 layer at the gate contact, the trapped charge density at the released silicon atoms may be given by [5]…”

“…δ is the thickness of the insulating layer, N d the doping concentration, φ m the work function of the metal, E g and χ are the band gap and electron affinity of the semiconductor respectively and N f is the density of fixed charges in the SiO 2 layer. The mathematical steps necessary to arrive at equation (3) are described in [1] and [2].…”

“…In some recent works [1,2] it has been shown that the dc characteristics of metal-semiconductor field effect transistors (MESFETs) can be better explained if one takes into account the interfacial oxide layer and interface states at the gate contact of the device. The drain characteristics and the threshold voltage of the device evaluated in [1,2] differ significantly from those obtained using conventional model calculations which ignore the above nonidealities. In this work it is shown that a MESFET structure with an interfacial layer may exhibit an ageing effect resulting from the interface reaction.…”

Effect of deep-level impurities on the drain characteristics of short-channel metal-semiconductor field effect transistors

“…The effect of the presence of trapping states on the electrical characteristics of metal-semiconductor field effect transistors has been the subject of considerable interest in the recent past [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. So far two types of state have been considered for the purpose of device modelling, namely, the deep-impurity states in the semiconductor [1][2][3][4] and interface states at the gate contact of the device [12][13][14]. The enhanced temperature sensitivity of the threshold voltage has been attributed to deep levels [1].…”

“…The models discussed in [3] and [4] include only the deep levels, though one cannot disregard the presence of interface states at the gate contact. The extent to which these devices are influenced by interface states has been discussed in a number of investigations [12][13][14]. One can therefore look for a further generalization by taking into account the presence of both the interface states and deep levels and study in depth the drain characteristics of the device.…”