Effect of Intrinsic Gettering on Semiconductor Device Performance in SOI Substrates

Abstract

This work investigates the effect of varying the structural characteristics of fusion-bonded thick SOI on the quality of oxides grown during fabrication of transistors using normal CMOS processing methods. The influences of the SOI device material, handle material and bonding procedure were examined using material supplied by various SOI vendors. In addition, the incorporation of gettering sites into the SOI layer near the interface with the buried oxide, was studied using buried implanted layers of various species. We found a strong influence of both the vendor and the position of the bonding interface on the quality of the surface thermal oxides, with handle-oxidised material giving superior gate oxides to device-oxidised SOI. A large improvement in oxide quality was shown by the introduction of the implanted ions, which was strongly dependent on the species, germanium giving the largest effect. This enabled the growth of high quality gate and tunnel oxides for electronic device fabrication. IntroductionSeveral techniques have conventionally been used to create gettering sites in silicon substrates on which semiconductor devices are fabricated (1). The methods include intrinsic gettering, in which thermal treatments are used to create both a defect-free zone at the surface of the substrate wafers, where the devices are formed, and a deeper, defective bulk area where impurities are gettered. Other techniques include extrinsic gettering, by providing a highly doped polysilicon layer on the back surface of the wafer or by creating mechanical damage on the back surface. Alternatively, a lightly doped epitaxial layer formed on a heavily doped substrate will provide gettering by segregation at the epitaxy-substrate interface.In SOI wafers, however, these types of gettering technique are not efficient, because the buried oxide layer acts as a barrier to prevent the diffusion of most types of impurity out of the active silicon region into the bulk and back surface of the wafer where the gettering sites are normally formed. Therefore, the impurities remain in the SOI region and will potentially degrade devices fabricated using standard semiconductor device manufacturing methods. It is possible that the degree of gettering of impurities in the SOI layer may be influenced by such factors as the SOI material, the position of the bonding interface and the fabrication method. One technique to overcome this is to provide a highly doped implanted gettering layer in the top surface of the SOI wafer, close to the devices, while another technique is to provide trenches around devices, which can getter impurities through mechanically-induced or stress-induced defect generation in the silicon material. However, both these methods have the disadvantage that substantial ECS Transactions, 3 (4) 469-480 (2006) 10.1149/1.2355779, copyright The Electrochemical Society 469 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 141.211.4.224 Downloaded on 2015-07-17 to...

Thick Bonded Silicon-On-Insulator Wafer with Polysilicon Interlayer for Gettering of Metal Impurities

“…Insufficient gettering of metal impurities is a fundamental problem on thick BSOI wafers. Transition metal contaminants in CMOS devices lead to oxide breakdown device failures and decrease in gate oxide integrity (1). silicon film on the backside of the wafer and substrates with high boron concentration for the case of extrinsic gettering and SiO 2 precipitates in the bulk of Czochralski (CZ) silicon wafers for the case of intrinsic gettering (IG) (2,3,4).…”

Thick Bonded Silicon-On-Insulator Wafer with Polysilicon Interlayer for Gettering of Metal Impurities

“…The buried oxide forms a diffusion barrier for most transition metals in silicon preventing the use of standard gettering methods common in conventional bulk silicon active devices [1]. Inadequate metal gettering in CMOS devices is known to lead to oxide breakdown device failures and decrease in gate oxide integrity (GOI) [2]. A new technique based on adding a thin polycrystalline silicon layer between the active layer and buried oxide for solving the aforementioned gettering problem in thick BSOI wafers is presented.…”